CFET Common-Gate Threshold Tuning With Dielectric Dipole Doping
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating multiple components efficiently while maintaining optimal threshold voltages for complementary field-effect transistors (CFETs), particularly in adjusting the threshold voltages of PFETs and NFETs with common gates.
Innovation Solution
The method involves forming CFETs with shared common p-type metal gates and adjusting threshold voltages by doping gate dielectrics of NFETs and PFETs with n-type and p-type dipole dopants, driving these dopants into the dielectrics through an anneal process, and forming a common gate electrode with a mid-gap work function to minimize manufacturing complexity and avoid damage to high-k dielectrics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etch-back processes are used to form common gates, then gate alignment is achieved, but high-k dielectrics are damaged
Solution Approach 1:
The patent applies preliminary action by forming the common gate structure before the high-k dielectric layers are fully processed. Specifically, a dummy gate is formed initially, then high-k dielectric layers are deposited over it, and finally the dummy gate is replaced with the actual common gate through a lift-off process. This sequence prevents etch-back damage to the high-k dielectrics while achieving proper gate alignment.
2Ease of manufacture
If separate gate electrodes are formed for NFETs and PFETs, then threshold voltage control is simplified, but device complexity increases
Solution Approach 1:
The patent merges the gate electrodes of NFETs and PFETs into a single common gate structure. The common gate is formed as one continuous electrode that serves both n-type and p-type transistors. Threshold voltage control is achieved not through separate gates but through selective dipole dopant doping of the high-k dielectric layers in different regions, thus reducing device complexity while maintaining manufacturing flexibility.
Solution Approach 2:
The patent applies local quality by introducing different dipole dopant concentrations in different spatial regions of the high-k dielectric layers. Specifically, n-type dipole dopants are introduced in NFET regions and p-type dipole dopants in PFET regions of the same common gate structure. This allows independent threshold voltage control for each transistor type despite sharing the same gate electrode.
3Manufacturing precision
If dipole dopants are introduced during gate dielectric formation, then threshold voltage tuning is achieved, but manufacturing steps increase
Solution Approach 1:
The patent applies preliminary action by introducing dipole dopants into the high-k dielectric layers during the initial dielectric formation process, before the actual gate electrode is created. The dipole dopants are incorporated into the high-k dielectric matrix during deposition, and then activated through a subsequent anneal process. This approach integrates threshold voltage tuning into the existing manufacturing flow without adding significant complexity.
Solution Approach 2:
The patent uses parameter changes by varying the concentration and type of dipole dopants introduced into the high-k dielectric layers. By controlling the dipole dopant concentration, the threshold voltage of the transistors can be precisely tuned. The anneal process temperature and duration are also optimized to achieve complete dopant activation while preventing unwanted diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise tuning of threshold voltages in CFETs, enhancing integration density and reducing manufacturing costs by avoiding etch-back processes that can damage high-k dielectrics, thereby improving the performance and efficiency of semiconductor devices.
Implementation Method 1
performing an anneal process to drive dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively
Data Source
AI summary
A method includes forming a first and a second gate dielectric on a first semiconductor channel region and a second semiconductor channel region overlapping the first semiconductor region, forming a first dipole film on the first gate dielectric, wherein the first dipole film comprises a first dipole dopant of a first type, and forming a second dipole film on the second gate dielectric. A drive-in process is performed to drive dipole dopants in the first dipole film and the second dipole film into the first gate dielectric and the second gate dielectric, respectively. The first dipole film and the second dipole film are removed. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric to form a first transistor and a second transistor.