CFET Through-Via Structure for Front-and-Back Interconnection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for higher transistor density in integrated circuits poses challenges in efficiently interconnecting complementary field-effect transistors (CFETs) across different layers and sides of a wafer.
Innovation Solution
The formation of a through-via structure that extends from the top surface of top FETs to the bottom level of bottom FETs, using a dielectric region etched to form an opening, which is then filled with a conductive material to facilitate electrical and signal interconnection between the front and backside of the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional interconnection methods are used for CFETs, then manufacturing process is simpler, but transistor density and interconnection efficiency are insufficient
Solution Approach 1:
The patent implements front-and-back interconnection by extending through-vias from the front surface through the substrate to the back surface, utilizing the third dimension (vertical depth) to create interconnection paths. This allows signals to route through the bulk substrate, effectively adding a vertical interconnection dimension that increases transistor density without planar congestion.
Solution Approach 2:
The through-via structure nests multiple functional elements within a single vertical feature: the via itself, dielectric liners for isolation, conductive fill material for electrical connection, and integration with both front-side and back-side contact structures. This nested arrangement maximizes interconnection efficiency within the available vertical space.
2Reliability
If through-via structure is implemented for front-and-back interconnection, then interconnection efficiency is improved, but manufacturing process complexity increases
Solution Approach 1:
The through-via formation process is segmented into distinct stages: front-side opening formation and filling, back-side opening formation and filling, and dielectric liner deposition. Each segment can be independently optimized and controlled, allowing complex through-via structures to be manufactured through manageable process steps with independent process control.
Solution Approach 2:
Dielectric liners are deposited as intermediary layers between the conductive via fill material and the surrounding semiconductor structures. These liners provide electrical isolation and mechanical stress relief, enabling reliable through-via formation while protecting adjacent devices from process damage and electrical interference.
3Reliability
If dielectric regions are used for isolation, then device isolation is achieved, but chip area utilization is reduced
Solution Approach 1:
Isolation functions are moved from the planar dimension to the vertical dimension through the use of dielectric liners deposited on the sidewalls of through-vias. This vertical isolation approach eliminates the need for large lateral dielectric regions, allowing chip area to be used more efficiently for active devices while maintaining proper electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient front-and-back interconnection of CFETs, reducing resistance and improving signal routing, while effectively utilizing the chip area occupied by the dielectric regions.
Implementation Method 1
The dielectric region is etched to form an opening therein
Data Source
AI summary
A method includes forming a first complementary Field-Effect Transistor (CFET) and a second CFET. The first CFET includes a first lower transistor, and a first upper transistor overlapping the first lower transistor. The second CFET includes a second lower transistor, and a second upper transistor overlapping the second lower transistor. The method further includes performing a first etching process to form a first opening, wherein the first etching process includes etching a first gate stack between the first upper transistor and the second upper transistor, and etching a second gate stack between the first lower transistor and the second lower transistor. The first opening is filled with a dielectric material to form a dielectric region. The method further includes performing a second etching process to etch a middle portion of the dielectric region and to form a second opening, and filling the second opening with a conductive material to form a through-via.