CFET Cell Rows With Selective Vertical Interconnects for Lower IR Drop
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Solution Overview
Problem
Existing integrated circuits face challenges in reducing IR drops and improving performance while maintaining the speed and current driving capabilities of transistors, particularly in stacked complementary field effect transistor (CFET) devices.
Innovation Solution
Implementing self-aligned vertical interconnects in some rows of circuit cells, specifically in tall cells, which are partially embedded in side-recesses and connect upper and lower conductor layers, while maintaining the integrity of short cells without such interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical interconnects are implemented in all circuit cells, then IR drops are reduced and performance is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies local quality by implementing vertical interconnects selectively only in tall cells where they are needed, rather than uniformly in all cells. This localized approach reduces IR drops in high-current tall cells while avoiding the complexity overhead in short cells, thereby resolving the contradiction between reliability improvement and device complexity increase.
Solution Approach 2:
The patent segments the circuit cell population into tall cells and short cells, applying different interconnect strategies to each segment. Tall cells receive vertical interconnects embedded in side-recesses, while short cells maintain conventional horizontal interconnects, thus reducing overall device complexity while still achieving IR drop reduction where necessary.
2Power
If vertical interconnects are implemented in tall cells, then current driving capabilities are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming side-recesses and preparing tall cell structures before implementing vertical interconnects. This advance preparation includes creating the side-recess geometry and positioning structures in earlier fabrication steps, which simplifies the subsequent vertical interconnect formation and reduces the precision requirements for the critical interconnect embedding step.
3Speed
If vertical interconnects are added to improve performance, then speed and current capabilities increase, but the integrity and speed of short cells may be compromised
Solution Approach 1:
The patent applies local quality by differentiating the interconnect structure between tall cells and short cells. Vertical interconnects embedded in side-recesses are implemented only in tall cells, while short cells maintain their conventional horizontal interconnect architecture, thereby preserving short cell integrity and performance while achieving speed and current capability improvements in tall cells.
Data Source
AI summary
An integrated circuit device with CFET devices includes tall cells in a first row and short cells in a second row. The integrated circuit device further includes one or more self-aligned vertical interconnects in the first row of tall cells. Each self-aligned vertical interconnect is at least partially embedded into a side-recess. The side-recess has a boundary surface conformally coated with insulation materials which terminate at least one gate-conductor intersecting an active-region structure in a tall cell. In the integrated circuit device, at least three short cells consecutively arranged in the second row are absence of any self-aligned vertical interconnect.