CFET Vertical Routing Structure for Compact Standard Cell Power
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Solution Overview
Problem
Conventional semiconductor technologies face challenges in further scaling down transistors to a few nanometers, particularly with silicon-based fabrication, which limits the miniaturization of integrated circuits and efficiency in routing power within complex standard cells.
Innovation Solution
The implementation of complementary field-effect transistor (CFET) structures with vertical routing structures, including a first and second FET of different charge carrier types, a frontside metal layer, a backside metal layer, and a vertical connector that electrically couples the backside metal conductor to the frontside metal conductor, allowing for efficient power routing without relying on higher-level metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional silicon-based fabrication is used for further transistor scaling, then manufacturing processes remain established and reliable, but the ability to miniaturize transistors to a few nanometers is limited
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertical stacking architectures. Multiple transistor layers are stacked vertically with interlayer vias connecting different levels, enabling continued miniaturization by utilizing the vertical dimension rather than only lateral scaling. This dimensional transition allows achieving smaller effective transistor footprints while remaining compatible with established silicon fabrication processes.
2Ease of operation
If higher-level metal layers are used for power routing in complex standard cells, then power distribution is achieved, but device complexity and routing overhead increase
Solution Approach 1:
The patent implements power and signal routing by utilizing vertical interlayer vias that connect different metal layers through the vertical dimension. Instead of relying solely on higher-level horizontal metal layers for power distribution, the design routes power vertically through stacked vias between adjacent metal layers, reducing the need for extensive higher-level routing and simplifying the overall metal layer structure.
Solution Approach 2:
The patent employs nested via structures where smaller vias are positioned within or adjacent to larger vias, allowing multiple routing functions to be integrated vertically. This nesting approach enables efficient use of vertical space for power and signal routing, reducing the number of discrete metal layers required while maintaining routing flexibility and power distribution efficiency.
Data Source
AI summary
Disclosed are complementary field effect transistor (CFET) circuits with vertical routing structures and methods for making the same. In an aspect, a semiconductor structure comprises a first field effect transistor (FET) of a first charge carrier type, comprising a first source/drain (S/D) region, a second S/D region, and a first gate; a second FET of a second charge carrier type, disposed above the first FET and comprising a third S/D region, a fourth S/D region, and a second gate; a frontside metal (FM) layer disposed above the second FET and comprising an FM conductor extending in an X direction; a backside metal (BM) layer disposed below the first FET and comprising a BM conductor extending in the X direction; and a vertical connector extending in the Z direction, that electrically couples the BM conductor to the FM conductor.