CFET Vertical Wall Structure for Accessing Stacked Transistors
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Solution Overview
Problem
The scaling of complementary field effect transistors (CFET) is limited by the requirement to access stacked transistors, which results in a significant portion of the area being reserved for power and signal routing, reducing the active area benefit.
Innovation Solution
A CFET structure with a vertical wall structure that includes a conductive core layer and a spacer layer, allowing electrical connections through openings, enabling a forksheet design that reduces the cell height and shares power rails between transistor stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are stacked vertically in CFET structure, then area scaling is improved (reduction of physical dimensions), but access to stacked transistors becomes difficult requiring outer-zone routing
Solution Approach 1:
The patent introduces a vertical wall structure with conductive core layers extending through the stacked transistor layers, enabling power and signal routing in the vertical dimension rather than only in the horizontal plane. This allows direct access to top transistors through the wall structure, eliminating the need for outer-zone routing while maintaining compact area.
Solution Approach 2:
The wall structure is segmented with openings that provide selective access to different transistor layers. The conductive core layer is divided into segments that can independently connect to bottom and top transistors, allowing separate routing paths for different functions and enabling direct access without outer-zone connections.
2Reliability
If symmetric CFET design with contact structures on both sides is used, then power supply to transistors is achieved, but cell height increases to approximately 4 tracks
Solution Approach 1:
The patent employs an asymmetric wall structure design where the wall is positioned to provide optimized access to both bottom and top transistors. The openings in the wall are asymmetrically arranged to directly connect power rails to both transistor types, achieving reliable power supply while reducing cell height to approximately 3.5 tracks compared to symmetric designs.
3Ease of operation
If outer-zone routing is used for bottom transistor connections, then transistor access is enabled, but active area ratio decreases to 37%
Solution Approach 1:
The patent moves routing from the horizontal outer-zone to the vertical dimension through the wall structure. Conductive core layers extend vertically through the transistor stack, allowing power and signal connections to be made through the active area rather than around it, thereby increasing the active area ratio while maintaining full transistor access.
Data Source
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AI summary
The disclosure relates to a complementary field effect transistor, CFET, structure (10). The CFET structure (10) comprises: a vertical wall structure (15); first transistor structure (21) comprising one or more first channel layers (11a), and a second transistor structure (22) comprising one or more second channel layers (12a), wherein the second transistor structure (22) is stacked on the first transistor structure (21); wherein the first and the second transistor structure (21, 22) are arranged on one side of the vertical wall structure (15), and wherein the first and the second channel layers (11a, 12a) are in contact with a side surface of the vertical wall structure (15). The vertical wall structure (15) comprises: a conductive core layer (13) and a spacer layer (14) which partially covers the conductive core layer (13) on the side surface of the vertical wall structure (15); wherein the spacer layer (14) has at least one opening to electrically connect the second transistor structure (22) with the conductive core layer (13).