CFET Via Fuse Structure for Dense Device Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional fuse layouts in CFETs require significant area, limiting the density of transistors in integrated circuits, and there is a need for a more efficient method to isolate devices from circuitry.
Innovation Solution
Incorporating a deep via fuse in the CFET device, which extends from the source/drain region to a buried conductive region, allowing for reduced area usage by functioning as a fuse to isolate devices, and formed through a sequential process involving etching and filling with metal, reducing the area required for fuses by up to 30%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fuse layouts are used in CFETs, then device isolation can be achieved, but the area required for fuses increases significantly
Solution Approach 1:
The patent transitions from planar fuse layouts to vertical 3D fuse structures by extending fuses through multiple interlayer dielectric layers and via holes, utilizing the vertical dimension to reduce footprint area while maintaining isolation functionality
Solution Approach 2:
The fuse structure is nested within the existing CFET vertical architecture, with fuses integrated through via holes that pass through interlayer dielectric layers, embedding the fuse function within the stacked device structure rather than occupying separate planar space
Data Source
AI summary
An embodiment includes a method including forming a first conductive feature and a second conductive feature in a substrate. The method also includes forming a first complementary field-effect transistor (CFET) over the substrate, the forming including forming a first lower transistor including a first gate and a first source/drain region. The method also includes forming a first upper transistor including a second gate and a second source/drain region, the first upper transistor overlapping the first lower transistor. The method also includes forming a conductive via fuse connected to the first conductive feature and the second source/drain region.