CFET Via Layout With Insulating Separation for Short-Circuit Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Vertical stacking of transistors in semiconductor devices leads to challenges such as short-circuits, higher resistances, and complex structure formation due to the need for vertical connecting structures, which are not effectively addressed by existing technologies.
Innovation Solution
The implementation of complementary field effect transistors (CFETs) with power and signal via structures that utilize larger, low-aspect-ratio PV structures and in-boundary power rails, avoiding gate-to-via spacing limitations and reducing the risk of short circuits by positioning signal vias at the ends of gate structures and using insulating structures to separate conductive elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical stacking of transistors is implemented to limit die area increase, then die area is reduced, but the risk of short-circuits increases and manufacturing complexity increases
Solution Approach 1:
The patent introduces an insulating structure as an intermediary element positioned between vertically-stacked transistors. This insulating structure acts as a mediator that prevents direct contact between conductive elements of adjacent transistors, thereby eliminating short-circuit paths while maintaining the compact vertical architecture. The insulating structure includes an insulating material that fills the space between transistor layers, providing electrical isolation without requiring increased lateral spacing.
Solution Approach 2:
The patent segments the vertical transistor structure into distinct layers separated by insulating structures. Each transistor layer is electrically isolated from adjacent layers through these insulating segments, allowing independent control and preventing unintended electrical interactions. This segmentation enables the vertical stacking to proceed without compromising reliability, as each segment is electrically independent.
2Area of stationary object
If vertical stacking of transistors is implemented to limit die area increase, then die area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of insulating structures with existing manufacturing processes by integrating them into the gate patterning sequence. The insulating structures are formed using the same lithography and etching steps that define gate structures, combining multiple functions into a unified process flow. This merging reduces the number of discrete manufacturing steps required compared to forming insulating structures separately.
Solution Approach 2:
The patent performs preliminary formation of insulating structures before final transistor assembly. By pre-positioning insulating materials in designated regions during earlier process stages, the patent simplifies subsequent steps where transistor layers are added. This preliminary action ensures that insulating barriers are already in place to guide and constrain the vertical stacking process, reducing complexity during critical assembly phases.
3Reliability
If conventional via structures are used to connect vertically-stacked transistors, then connection is achieved, but resistance increases and short-circuit risk increases
Solution Approach 1:
The patent transitions from conventional planar via connections to three-dimensional contact structures that extend vertically through multiple transistor layers. These contact structures are formed as elongated conductive elements that penetrate through insulating and conductive layers in the vertical dimension, enabling direct electrical connection between stacked transistors without requiring tight lateral spacing. This dimensional change allows connections to be made at multiple vertical levels simultaneously.
Solution Approach 2:
The patent implements nested conductive and insulating structures where contact regions are positioned within and between transistor layers. The contact structures are nested within the vertical stack, with conductive elements embedded in insulating matrices that are themselves nested within the transistor architecture. This nesting arrangement allows multiple connections to be made in a compact volume without increasing lateral footprint or reducing spacing margins.
Data Source
AI summary
A semiconductor device includes a plurality of first gate structures arranged along a first direction and extending in a second direction, at least one first gate structure of the plurality of first gate structures corresponding to a first transistor region; a plurality of second gate structures arranged along the first direction and aligned with ones of the first gate structures in the second direction, at least one second gate structure of the plurality of second gate structures corresponding to a second transistor region; an insulating structure extending in the second direction and separating the plurality of first gate structures from the plurality of second gate structures; and a first conductive via in the insulating structure and configured to carry a signal for the first transistor region.