CFET Via Structure With Single Damascene for Lower Parasitic Resistance
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling transistors to smaller sizes due to limitations in three-dimensional integration, particularly in forming wide backside power rails and incorporating signal wiring without increasing parasitic resistances and edge placement errors.
Innovation Solution
A method involving bonding wafers with alternating epitaxial layers to form stacked transistors, creating a power delivery network with backside power rails and signal wiring, allowing for wider power rails and improved connectivity by removing residual FIN structures and using conductive materials for vias and interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional circuit scaling is continued, then transistor density increases, but parasitic resistances increase and manufacturing challenges worsen
Solution Approach 1:
The patent transitions from two-dimensional circuit layout to three-dimensional integration by bonding multiple wafers with alternating epitaxial layers, stacking transistors vertically. This dimensional change allows continued transistor density improvement without the parasitic resistance penalties of planar scaling.
Solution Approach 2:
The patent divides the semiconductor structure into multiple discrete wafers that are bonded together, with each wafer containing specific transistor tiers. This segmentation enables independent optimization of each layer and facilitates the formation of wide backside power rails that reduce parasitic resistance.
2Power
If wide backside power rails are formed in conventional processes, then power delivery improves, but manufacturing complexity and edge placement errors increase
Solution Approach 1:
The patent forms wide backside power rails during the wafer bonding process itself, before subsequent transistor fabrication steps. This preliminary action simplifies manufacturing by establishing the power delivery network early, avoiding complex later modifications and reducing edge placement errors.
Solution Approach 2:
The bonding dielectric layer serves multiple functions: it provides electrical isolation between stacked transistors, enables the formation of wide backside power rails, and facilitates wafer bonding. This multi-functionality reduces manufacturing complexity by consolidating multiple requirements into a single structural element.
3Adaptability or versatility
If signal wiring is incorporated in stacked transistor structures, then connectivity improves, but parasitic resistances increase
Solution Approach 1:
The patent removes residual FIN structures from specific locations to uncover bonding dielectric, creating localized contact regions for signal wiring. This local quality approach allows signal routing without requiring wide traces that would increase parasitic resistance, maintaining connectivity while minimizing harmful effects.
Solution Approach 2:
The bonding dielectric layer acts as an intermediary that enables signal wiring through controlled removal regions. By serving as both the bonding medium and the isolation layer, it facilitates connectivity while maintaining electrical separation, thus reducing parasitic resistance between stacked transistor tiers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased transistor density and reduced parasitic resistances, facilitating more efficient power delivery and signal transmission in semiconductor devices.
Implementation Method 1
bonding a first wafer to a second wafer via a first bonding dielectric layer
Implementation Method 2
a first stack of alternating layers of epitaxially grown semiconductor layers formed over a second bulk semiconductor material
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first tier of transistors on a first bonding dielectric layer on a first bulk semiconductor material. A second tier of transistors is formed on a second bonding dielectric layer over the first tier of transistors. The second bonding dielectric layer separates the first tier of transistors from the second tier of transistors. The first tier of transistors and the second tier of transistors have gate-all-around transistors. First via openings are formed that extend through the first tier of transistors and the first bonding dielectric layer. First local interconnect (LI) openings are formed that connect with the first via openings. Second via openings are formed that extend through the second tier of transistors, the second bonding dielectric layer, the first tier of transistors and the first bonding dielectric layer. Second LI openings are formed that connect with the second via openings.