CFET VLI Hard Mask Structure for Gate Height Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the large metal area occupied by the vertical local interconnect (VLI) structure in complementary field-effect transistors (CFETs), leading to increased capacitance and decreased speed performance, particularly due to the use of thick hard mask layers that cause gate height variations and prolonged processing times.
Innovation Solution
A sandwich-like hard mask layer is employed, comprising a thin bottom mask layer, a polish stop layer, and a protective layer, with controlled polishing rates to precisely stop at the polish stop layer, preventing unintended damage to the VLI structure and gate height variation, using amorphous silicon for the polish stop layer and oxygen-free materials to prevent oxidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick hard mask layer is used to protect the VLI structure during processing, then the VLI structure is better protected from damage, but the gate height varies and processing time increases
Solution Approach 1:
The hard mask layer is divided into multiple segments: a first hard mask layer (thicker, provides protection), a second hard mask layer (thinner, enables precise polishing control), and a third hard mask layer (protective layer). This segmentation allows the system to simultaneously achieve VLI structure protection through the first layer and precise gate height control through the second layer's controlled polishing rate.
Solution Approach 2:
The patent utilizes different polishing rates for different hard mask layer materials as the key parameter change. The second hard mask layer is specifically selected to have a controlled polishing rate that is slower than the first hard mask layer but faster than the underlying layer, enabling it to serve as a polishing stop layer that prevents over-polishing and gate height variation while still allowing effective VLI structure protection.
2Reliability
If a thick hard mask layer is used to protect the VLI structure, then protection is improved, but processing time increases
Solution Approach 1:
The multi-layer hard mask structure segments the protection function across different layers with different thicknesses and polishing rates. The thinner second hard mask layer with controlled polishing rate provides sufficient protection while reducing the total polishing time compared to a uniformly thick hard mask layer, as it allows more selective and faster removal of the first hard mask layer.
Solution Approach 2:
The second hard mask layer acts as an intermediary polishing stop layer between the first hard mask layer (protective function) and the underlying layers. This intermediary layer enables controlled polishing processes that remove the first layer efficiently while preventing damage to underlying structures, thereby reducing overall processing time while maintaining protection.
3Reliability
If the VLI structure occupies large metal area, then electrical connection is ensured, but capacitance increases and speed performance decreases
Solution Approach 1:
The patent changes the physical and chemical parameters of the hard mask layers, particularly the polishing rates of different materials. By selecting materials with specific polishing rate relationships (second layer slower than first, but faster than underlying layers), the process achieves precise control over the VLI structure dimensions, allowing minimization of metal area while maintaining adequate electrical connection and improving speed performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the VLI area, minimizing capacitance and improving speed performance by maintaining precise gate heights and reducing processing time, resulting in a more efficient and compact CFET design.
Implementation Method 1
with controlled polishing rates to precisely stop at the polish stop layer
Implementation Method 2
using amorphous silicon for the polish stop layer and oxygen-free materials to prevent oxidation
Data Source
AI summary
A method includes a number of operations. A bottom transistor and a top transistor overlapping the bottom transistor are formed. A vertical local interconnect (VLI) structure is formed and electrically connects source/drain regions of the bottom transistor and the top transistor. A hard mask layer is formed over the VLI structure, wherein the hard mask layer includes a bottom nitride layer, a top nitride layer and an amorphous semiconductive layer directly between the bottom nitride layer and the top nitride layer. The hard mask layer is patterned. A trench is formed in the VLI structure. An isolation structure is formed in the trench. A first polishing process is performed to the isolation structure and the hard mask layer, wherein the first polishing process stops the amorphous semiconductive layer. A second polish process is performed to the isolation structure, the bottom nitride layer and the amorphous semiconductive layer.