CFET Wafer Bonding for Dense Local Interconnect Integration
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Solution Overview
Problem
Current technologies face challenges in increasing the density of transistors in integrated circuits, particularly in forming complementary Field-Effect Transistors (CFETs) with efficient local interconnects, as existing methods lack flexibility in materials and structures for upper and lower transistors.
Innovation Solution
The formation of CFETs through sequential or parallel processes, allowing for flexibility in materials and structures of upper and lower transistors, including different surface orientations and types such as Gate-All-Around (GAA) and Fin Field-Effect Transistors (FinFETs), with local interconnects formed using various semiconductor materials and processes like face-to-back and back-to-back bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional planar transistor structures are used, then manufacturing processes are simple, but transistor density cannot meet increasing demands
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertical structures, including FinFETs with vertical channels and GAA transistors with nanosheets stacked vertically. This dimensional change enables significantly higher transistor density by utilizing the vertical space above the substrate, allowing multiple active channels to be packed into a smaller footprint area while maintaining manufacturability through established semiconductor fabrication processes adapted for vertical geometries
Solution Approach 2:
The patent implements nested structures where gate electrodes wrap around channel regions in Gate-All-Around (GAA) transistors, providing complete gate control. The gate structure is nested within and around the vertical channel, enabling superior electrostatic control and higher density compared to planar structures. This nested configuration allows the transistor to achieve higher packing density while maintaining effective gate control over the channel
2Quantity of substance
If CFETs with overlapping upper and lower transistors are formed, then transistor density increases, but interconnect formation becomes more challenging
Solution Approach 1:
The patent divides the CFET structure into distinct upper and lower transistor regions with separate source/drain areas. Local interconnect structures are segmented to selectively connect specific upper transistor source/drain regions to corresponding lower transistor regions. This segmentation enables precise electrical connections while maintaining the overlapping vertical configuration, allowing complex interconnect routing to be broken down into manageable discrete connection points that can be formed using standard via and contact processes
Solution Approach 2:
The patent introduces local interconnect structures as intermediary elements between the upper and lower transistor regions. These interconnects act as mediators that facilitate electrical coupling between the overlapping transistor regions without requiring direct physical contact between source/drain regions. The local interconnects can be formed as conductive vias or contact structures through dielectric layers, simplifying the manufacturing process by decoupling the geometric overlap requirement from the electrical connection requirement
3Reliability
If flexible material selection for upper and lower transistors is implemented, then performance optimization improves, but manufacturing process complexity increases
Solution Approach 1:
The patent enables different material compositions and structural configurations for upper and lower transistor regions to optimize performance for specific conductivity types (n-type or p-type). Each transistor region can be independently tailored with appropriate semiconductor materials, gate dielectrics, and contact structures based on its functional requirements. This local quality approach allows n-type transistors to use materials optimized for electron transport while p-type transistors use materials optimized for hole transport, achieving superior device performance without requiring complete process redesign
Solution Approach 2:
The patent allows variation of critical parameters including material composition, doping concentrations, channel dimensions, and gate structures between upper and lower transistors. These parameter changes enable optimization of threshold voltage, drive current, and subthreshold swing for each transistor region independently. By adjusting these parameters within established process capabilities, the patent achieves enhanced transistor performance while maintaining compatibility with existing semiconductor manufacturing infrastructure
Data Source
AI summary
A method includes forming a first transistor in a first wafer, wherein the first transistor includes a first source/drain region, forming a first bond pad electrically coupling to the first source/drain region, forming an second transistor in a second wafer, wherein the second transistor includes a second source/drain region, forming a second bond pad electrically coupling to the second source/drain region, and bonding the second wafer to the first wafer, with the second bond pad being bonded to the first bond pad.