CFET Wire Pair Layout for Dense Gate-All-Around Scaling
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Solution Overview
Problem
As the semiconductor industry advances to nanotechnology process nodes, there is a need to improve gate-all-around complementary field effect transistors (CFETs) to reduce transistor size below 10-15 nm, while maintaining high device density, performance, and reducing the short-channel effect.
Innovation Solution
The semiconductor device features a substrate with a first and second conductive layer, each comprising wire pairs with common and non-common ends, and a shared gate structure surrounding channel structures, allowing for efficient electrical connections and reduced process complexity through the formation of closed patterns and alternating arrangements of wire pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced to below 10-15 nm to increase device density, then integration degree is improved, but manufacturing precision and control of short-channel effect become more difficult
Solution Approach 1:
The patent transitions from planar transistor architecture to three-dimensional gate-all-around CFET structure with vertically stacked NFET and PFET channels. This dimensional change enables continued scaling at nanometer nodes by utilizing vertical space, thereby maintaining device density improvements while managing the complexities of miniaturization through enhanced gate control in multiple directions.
2Reliability
If gate-all-around CFET structure is implemented to reduce short-channel effect, then transistor performance is improved, but device complexity increases
Solution Approach 1:
The patent merges NFET and PFET channels into a vertically stacked configuration sharing a common gate structure. This consolidation achieves superior electrostatic control and reduced short-channel effects by surrounding both channel types with the gate, while simultaneously reducing overall device footprint and interconnect complexity compared to separate planar implementations.
Solution Approach 2:
The shared gate structure in the gate-all-around CFET serves multiple functions: it controls both NFET and PFET channels, provides electrostatic isolation between opposite-type transistors, and enables compact vertical stacking. This multi-functionality reduces the number of separate gate structures needed, thereby managing device complexity despite the advanced three-dimensional architecture.
3Device complexity
If wire pairs with common end and non-common end are used to reduce connecting wires, then manufacturing process complexity is reduced, but wire pair pattern precision requirements increase
Solution Approach 1:
The patent employs asymmetric wire pair configurations where one end of adjacent wire pairs is connected (common end) while the other end remains separate (non-common end). This asymmetric design reduces the total number of independent connecting wires needed in the conductive layers, simplifying the interconnect structure and manufacturing process, while the asymmetry itself becomes a defining characteristic of the wiring pattern.
Data Source
AI summary
The present disclosure provides a semiconductor device and a method for manufacturing a semiconductor device. Every two first wires of a first conductive layer of the semiconductor device have a common end, and every two second wires of a second conductive layer of the semiconductor device have a common end.