CFET Wrap-Around Contact Structure for Low-Resistance BPR Connection
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Solution Overview
Problem
The challenge in manufacturing complementary field effect transistors (CFETs) lies in forming reliable electrical connections between buried power rails (BPR) and source or drain epitaxial growths, particularly due to the complexity of 3D stacking, which results in high resistance contacts.
Innovation Solution
A method involving silicon epitaxial growth, addition of contact and conductive materials, and etching to form a wrap-around contact that connects the BPR to the source or drain epitaxial growth, using materials like Ti, Ruthenium, and Tungsten to achieve low resistance connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used in CFET manufacturing, then the manufacturing process is simpler, but the contact resistance is high
Solution Approach 1:
The patent transitions from planar contact formation to three-dimensional wrap-around contact structure. The conductive material wraps around the epitaxial growth in vertical and lateral dimensions, creating a multi-dimensional contact path that increases contact area and reduces resistance while managing the complexity through structured 3D geometry.
Solution Approach 2:
The wrap-around contact structure embeds multiple layers of conductive material and epitaxial growth within each other in a nested configuration. The conductive material is positioned between and around different epitaxial layers, creating a nested arrangement that maximizes contact area while maintaining structural integrity.
2Area of stationary object
If wrap-around contact structure is formed, then contact area is maximized, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the conductive material and epitaxial growth in a specific sequence before final contact formation. The conductive material is deposited and patterned in advance, and epitaxial growth is performed to specific thicknesses and doping levels beforehand, enabling the wrap-around structure to be formed with controlled contact area while managing process complexity through staged fabrication.
3Reliability
If epitaxial growth is performed with specific doping, then electrical performance is improved, but manufacturing variability increases
Solution Approach 1:
The patent employs parameter changes by varying doping concentrations, epitaxial growth temperatures, and thickness parameters across different layers and regions. Specific doping levels (e.g., 1E19 to 1E21 atoms/cm³) and growth conditions are optimized to achieve desired electrical performance while controlling variability through precise parameter specification and process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of robust, low-resistance electrical connections between the BPR and the source or drain epitaxial growth, enhancing the yield and performance of CFET devices by maximizing the contact area and reducing manufacturing variability.
Implementation Method 1
performing silicon epitaxial growth in a lower level of an unfinished CFET structure to form at least one of a source and a drain
Data Source
AI summary
A method of forming an electrical connection between a buried power rail (BPR) of an unfinished complementary field effect transistor (CFET) and a source or drain epitaxial growth of a lower level of the CFET is provided. The method includes performing silicon epitaxial growth in a lower level of the CFET, adding a contact material to a portion of an exposed portion of the silicon epitaxial growth in the lower level, the exposed portion of the silicon epitaxial growth being located in a vertical slot of the unfinished CFET structure, adding a conductive material within a vertical channel, the conductive material being in contact with the added contact material and the BPR to form an electrical connection between the portion of the exposed portion of the silicon epitaxial growth and the BPR and etching back a portion of the added conductive material within the vertical channel.