Multi-Stage CFR Processing for Low Sampling Rate Peak Removal
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Solution Overview
Problem
Conventional Crest Factor Reduction (CFR) methods in communication devices, such as repeaters, are ineffective in removing peak components when the sampling position does not match the peak position of the input signal, leading to residual peaks exceeding the threshold, especially at low sampling rates, due to processing speed limitations of field programmable gate arrays (FPGAs).
Innovation Solution
A communication device employing multiple CFR modules with a sample shifter that shifts the first processed signal by a preset time, allowing the second CFR module to process the signal at a different time, effectively removing peak components even at low sampling rates, thereby matching the sampling and peak positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling rate is increased to match sampling position with peak position, then peak removal accuracy is improved, but FPGA processing speed capability is exceeded or high-end FPGA is required
Solution Approach 1:
The patent divides the CFR processing into multiple stages with different sampling rates. The first CFR module uses a lower sampling rate for initial peak removal, while the second CFR module uses a higher sampling rate for residual peak elimination. This segmentation allows the system to achieve high peak removal accuracy without requiring the entire processing chain to operate at the highest sampling rate, thus avoiding FPGA processing speed limitations.
Solution Approach 2:
The patent dynamically adjusts the sampling rate based on the processing stage and residual peak characteristics. By using different sampling rates in different stages, the system adapts its behavior to optimize both speed and accuracy. The first stage operates at a lower sampling rate for speed efficiency, while the second stage operates at a higher sampling rate for accuracy, making the overall system dynamic and adaptable.
2Reliability
If multistage CFR method is used to reduce remaining peak signal, then peak removal completeness is improved, but FPGA logic capacity increases excessively
Solution Approach 1:
The patent segments the CFR processing into two distinct modules with different functional focuses. The first CFR module handles the bulk of peak removal using a lower sampling rate, while the second CFR module addresses residual peaks using a higher sampling rate. This segmentation reduces the logic capacity requirement for each individual module compared to a single-stage system that would need to handle all peaks at high resolution.
Solution Approach 2:
The patent changes the sampling rate parameter between the two CFR modules to optimize the balance between peak removal completeness and FPGA logic capacity. By using a lower sampling rate in the first stage and a higher sampling rate in the second stage, the system achieves complete peak removal without requiring excessive logic capacity throughout the entire processing chain.
Data Source
AI summary
The present disclosure relates to a method of reducing a Peak to Average Power Ratio (PAPR) in a communication device, and more particularly, to a method of Crest Factor Reduction (CFR) processing of a signal in order to reduce a PAPR in a communication device such as a repeater. The communication device includes: a first CFR module configured generate a first processed signal by CFR processing an original signal; and a second CFR module configured generate a second processed signal by CFR processing the first processed signal, wherein the first processed signal is generated using a first sampling rate, and the second processed signal is generated using a second sampling rate. According to the disclosure, even a communication device with a low sampling rate may effectively remove a peak component of an input signal.