CGR Buffer Topology Selection for Dataflow Routing
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Solution Overview
Problem
Traditional compilers for Von Neumann computer architectures are inadequate for executing high-level programs requiring massively parallel computations, such as those for machine learning and artificial intelligence, as they lack the ability to efficiently pipeline computations, route data between compute units, and synchronize operations in dataflow graphs with nested loops.
Innovation Solution
A method is introduced to transform high-level programs into configuration data for reconfigurable data processors, which involves identifying skip buffers and determining the lowest cost implementation topology for buffer implementation, including cascaded, hybrid, and striped buffer topologies, to optimize data routing and synchronization in coarse-grained reconfigurable architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is routed through multiple pipeline stages in a reconfigurable architecture, then parallel processing capability is improved, but routing channel congestion increases
Solution Approach 1:
The patent segments the buffer implementation into multiple topologies (cascaded, hybrid, striped) that can be selected based on specific dataflow requirements. Each topology divides the buffering function into different structural components, allowing data to be routed through segmented paths rather than single congested channels, thereby reducing routing channel congestion while maintaining parallel processing capability.
2Adaptability or versatility
If skip buffers are used to store data for downstream stages, then data skipping capability is improved, but buffer depth requirements increase
Solution Approach 1:
The patent implements dynamic buffer management where the buffer depth and topology are not fixed but can be configured based on the specific dataflow graph requirements. The compiler analyzes the dataflow graph to determine optimal buffer depths for skip buffers, allowing the system to adapt buffer resources to actual needs rather than provisioning for maximum possible depth in all cases, thus reducing overall buffer depth requirements while maintaining data skipping capability.
Solution Approach 2:
The patent changes the parameter of buffer implementation from a single fixed-depth buffer to multiple buffers with variable depths organized in different topologies. By parameterizing the buffer depth based on specific skip requirements in the dataflow graph, the system can minimize buffer depth for each specific skip operation rather than using a conservative maximum depth for all operations.
3Device complexity
If traditional Von Neumann architecture is used, then compiler simplicity is maintained, but execution efficiency for parallel computations deteriorates
Solution Approach 1:
The patent introduces a specialized compiler component that acts as an intermediary between the high-level program and the reconfigurable architecture. This compiler translates the program into a dataflow graph representation and then maps it to the reconfigurable hardware, handling the complexity of parallel execution, pipeline staging, and buffer management. This intermediary layer preserves relative compiler simplicity while enabling efficient parallel execution on the reconfigurable architecture.
Solution Approach 2:
The patent performs preliminary analysis and transformation of the high-level program into a dataflow graph before code generation for the reconfigurable architecture. This preliminary action includes identifying parallel operations, determining pipeline stages, and planning buffer requirements, which prepares the computation in advance for efficient parallel execution. By doing this analysis upfront, the system can optimize execution efficiency without requiring complex runtime decisions.
Data Source
AI summary
A system and method for transforming a high-level program into configuration data for a coarse-grained reconfigurable (CGR) data processor with an array of CGR units. The high-level program is transformed into a dataflow graph that includes multiple interdependent asynchronously performing meta-pipelines. A first buffer is identified that stores data that is passed from a producer in a first meta-pipeline stage to a consumer in a second meta-pipeline stage. The system determines limitations associated with the array, and selects for implementation the lowest-cost buffer topology, chosen from a cascaded buffer topology, a hybrid buffer topology, and a striped buffer topology, where cost is determined by the number of memory units and on a number of times data is written into a memory unit while traveling through the first buffer. Optimal configuration data for the array is generated and stored.