CGR Hypersections for Faster Computational Graph Compilation and Execution
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Solution Overview
Problem
Interpreted languages executing large computing graphs on traditional hardware face performance issues due to the increasing number of sections to map, leading to slowed execution.
Innovation Solution
The technology identifies hypersections in the computing graph and compiles and executes them efficiently using a coarse-grained reconfigurable (CGR) processor, grouping operations into hypersections to share mapping and reduce execution time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the computing graph is divided into many small sections for mapping to hardware, then the execution can be performed, but the number of sections increases leading to slower interpreter execution
Solution Approach 1:
The patent combines multiple small code sections into larger hypersections that can be executed as unified units. By merging adjacent sections that share common operations and data flows, the system reduces the total number of sections the interpreter must manage, thereby improving execution speed while maintaining hardware mapping capabilities.
Solution Approach 2:
The patent segments the computing graph into hypersections at an optimal granularity level. Rather than using fine-grained small sections, the segmentation strategy creates coarser hypersections that group related operations together, reducing overhead while preserving the ability to map to hardware efficiently.
2Productivity
If the computing graph is divided into smaller segments (hypersections), then compilation speed and throughput are enhanced, but the graph structure becomes more complex to manage
Solution Approach 1:
The patent applies segmentation by dividing the computing graph into hypersections at strategic points where operations can be independently compiled and executed. This segmentation enables parallel compilation of multiple hypersections, improving overall compilation speed while the modular structure makes the graph easier to manage through clear boundaries and dependencies.
Solution Approach 2:
The patent performs preliminary analysis to identify common patterns and repeated operations within the computing graph before creating hypersections. By pre-identifying optimization opportunities and grouping operations that can share hardware resources, the system enhances compilation speed without creating unnecessary structural complexity.
Data Source
AI summary
The present disclosure provides a method and system for efficiently compiling and executing a high-level program (e.g., artificial intelligence models) on a coarse-grained reconfigurable (CGR) processor comprising an array of CGR units. In one aspect, the system identifies a first occurrence of a section of code within the high-level program, and then creates a first instance of a hypersection based on the section of code. The system next identifies a subsequent occurrence of the section of code within the high-level program, and subsequently creates a second instance of the hypersection based on the section of code. Next, the system compiles the high-level program including the first and second instance of the hypersection. Subsequently, the system executes the high-level program including the first and second instance, which repeatedly executes the section of code. Segmenting the high-level program based on one or more pre-defined hypersections increases both compilation speed and compiler throughout.