CGR Processor Token Synchronization for Consistent Execution States
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Solution Overview
Problem
Existing parallel processing architectures face challenges in synchronizing the execution of computation and dataflow graphs across multiple coarse-grained reconfigurable processors, leading to inefficiencies and inconsistencies in program load and termination times.
Innovation Solution
Implementing a synchronization mechanism using token interfaces and address generator and coalescing units (AGCUs) to manage the execution start and termination of programs across multiple CGR arrays, with a hierarchical protocol involving system, processor, and array master AGCUs to ensure synchronized execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple CGR processors execute programs independently without synchronization, then each processor can operate autonomously and efficiently, but execution times and program load/termination become inconsistent across processors
Solution Approach 1:
The patent introduces token interfaces as intermediary components that mediate communication between CGR processors. These token interfaces receive, store, and transmit synchronization tokens between processors, enabling coordinated execution start and termination while maintaining autonomous operation. The token interface acts as a buffer and communication channel that reconciles independent processor operations with synchronized execution requirements.
Solution Approach 2:
The synchronization mechanism employs feedback loops where processors monitor execution states and exchange status tokens. The system continuously monitors program load status, execution progress, and termination conditions, adjusting token transmission and processing accordingly. This feedback enables dynamic synchronization that adapts to varying execution conditions while maintaining consistency across the parallel processing system.
2Reliability
If a synchronization mechanism is implemented across multiple CGR processors, then execution consistency is improved, but system complexity increases due to additional coordination overhead
Solution Approach 1:
The synchronization system is segmented into hierarchical levels: individual CGR processors, token interfaces, and a master controller. Each segment handles specific synchronization tasks independently, reducing the complexity burden on any single component. The segmentation allows distributed synchronization where local decisions can be made at each level without requiring centralized control for every operation.
Solution Approach 2:
The patent introduces a temporal dimension to synchronization through token-based coordination. Instead of attempting to synchronize all processors simultaneously in space, the system uses sequential token passing and staged execution control across time. This temporal dimensionality allows complex synchronization to be broken into manageable phases, reducing the apparent system complexity.
3Speed
If tokens are stored in FIFO memory independent of array readiness, then communication efficiency between processors is improved, but potential latency is introduced when the array is not ready to receive
Solution Approach 1:
The token interface stores incoming synchronization tokens in FIFO memory in advance, before the CGR array is ready to process them. This preliminary action ensures that tokens are already available and buffered when the array becomes ready, eliminating waiting time and ensuring immediate processing can begin once the array is prepared.
Solution Approach 2:
The FIFO memory structure provides a cushioning buffer that absorbs timing variations between token generation and array readiness. This beforehand cushioning protects the system from latency by ensuring tokens are preserved and ready for immediate transmission once the array becomes available, smoothing out temporal discrepancies in the synchronization process.
Data Source
AI summary
A system includes a first coarse-grained reconfigurable (CGR) processor including first and second CGR arrays. A second CGR processor includes third and fourth CGR arrays. Each CGR array includes an address generator and coalescing unit (AGCU) designated as an array master AGCU (AMAGCU). The first CGR array AGCU is also designated as a processor master AGCU (PMAGCU) and as a system master (SMAGCU). The third CGR array AGCU is also designated as a PMAGCU. Each AMAGCU performs first execution synchronization actions, each PMAGCU also performs second execution synchronization actions, and the SMAGCU also performs third execution synchronization actions. The execution synchronization actions include a token exchange protocol for tokens such as “array ready”, “processor ready”, “system master ready”, “program start”, “array done, “processor done”, and “program terminate”. The tokens are communicated over a token bus via token interfaces that include a bus interface and a token receive FIFO.