CGRA Assembly Language Data Flow Graph Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional compilation tools face challenges in programming operations for new architectures like the Streaming Engine (SE) implemented using a Coarse Grained Reconfigurable Array (CGRA), as they require precise scheduling of instructions across tiles to maintain synchronous data flows, which is difficult to achieve with traditional assembly language-based approaches.
Innovation Solution
An innovative assembly language is developed that describes programs as graphs representing data flows, allowing for the specification of dispatch interface, memory interface, and tile memory operations, enabling efficient execution on CGRA by mapping instructions to tiles with proper timing alignment through a scheduler and software tool.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional assembly language programming is used with virtual registers mapped to physical registers, then register reuse can be implemented, but the programming complexity and difficulty of scheduling increase significantly for CGRA architectures
Solution Approach 1:
The patent introduces an intermediary layer (the novel assembly language syntax and compiler infrastructure) between the programmer and the physical hardware registers. Instead of directly mapping virtual registers to physical registers as in traditional approaches, the system uses an intermediate representation that automatically handles the mapping and scheduling, thereby reducing programming complexity while maintaining register reuse capabilities
Solution Approach 2:
The patent replaces the manual mechanical process of register allocation and scheduling with an automated compiler-based system. The compiler automatically performs register allocation, instruction scheduling, and data flow analysis, substituting the complex manual mechanical process with an automated software-based approach that simplifies programming
2Productivity
If instructions are precisely scheduled across tiles to maintain synchronous data flows, then execution efficiency improves, but the difficulty of programming and compilation increases
Solution Approach 1:
The patent applies preliminary action by performing instruction scheduling and tile assignment during the compilation phase rather than during runtime or manual programming. The compiler pre-analyzes the data flow graph and determines the optimal execution schedule and tile mapping in advance, generating optimized code that maintains synchronous data flows without requiring the programmer to manually handle the complex scheduling details
Solution Approach 2:
The patent segments the programming task into two distinct parts: high-level algorithm description (done by the programmer) and low-level scheduling optimization (done automatically by the compiler). This segmentation allows programmers to focus on algorithm correctness while the compiler handles execution optimization, thereby improving execution efficiency without increasing programming difficulty
3Ease of manufacture
If traditional compilation tools are used for CGRA architectures, then existing toolchains can be leveraged, but precise scheduling and timing alignment cannot be achieved
Solution Approach 1:
The patent introduces dynamic scheduling capabilities to traditional compilation tools by implementing a novel assembly language with explicit timing constructs and data flow annotations. The compiler dynamically analyzes the data flow graph and generates timing-aligned instructions for parallel execution on multiple tiles, thereby achieving precise scheduling while extending existing toolchain capabilities rather than requiring complete replacement
Data Source
AI summary
Control a coarse grained reconfigurable array during execution of an assembly language program identifying data flows through memory locations represented by memory variables. For example, a lowering program can be configured to receive the assembly language program, a hardware profile of the coarse grained reconfigurable array, and an instruction execution schedule to generate a configuration usable to control the coarse grained reconfigurable array. The lowering program can identify tile memories used to implement the memory locations represented by the memory variables in the assembly language program, and trace the data flows specified in the assembly language program. Using timing of instruction execution identified in the schedule, the lowering program can determine timing and controls for the dispatch interface, memory interfaces, and internal connections within tiles of the coarse grained reconfigurable array during execution of the assembly language program.