CGRA Dataflow Graph Synchronization for Variable-Latency Pipelines
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Solution Overview
Problem
Existing methods fail to synchronize data in a pipeline, where existing hardware design to support variable latency instructions for resource efficiency, higher throughput, and pipelining efficiency, but input operands to each stage need to be delayed by the same amount to produce correct pipelined results, which can be costly for resource-restricted hardware.
Innovation Solution
A compiler-based synchronization method for processors with variant stage latencies, such as reconfigurable architectures, uses on-chip registers and latch-based FIFOs to synchronize data across stages with varying latencies, ensuring correct pipelined results without excessive resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-chip registers are used to delay input operands to match the delay of other operands, then correct pipelined results are produced, but hardware resource cost increases significantly
Solution Approach 1:
The patent segments the delay requirement into two parts: (1) instruction-level delay handled by standard pipeline registers, and (2) operand-level delay handled by a separate synchronization mechanism using available registers efficiently. This segmentation allows the system to meet timing requirements without allocating excessive registers solely for synchronization.
Solution Approach 2:
The patent introduces a compiler-based synchronization mechanism that acts as an intermediary between the instruction stream and the hardware pipeline. The compiler analyzes data dependencies and inserts synchronization instructions that coordinate operand availability without requiring dedicated hardware synchronization circuits, thus reducing overall register usage.
2Productivity
If variable latency instructions are supported for resource efficiency, then throughput and pipelining efficiency improve, but data synchronization complexity increases
Solution Approach 1:
The patent implements a self-service synchronization mechanism where the compiler automatically analyzes data dependencies between instructions with variable latencies and generates appropriate synchronization code. This eliminates the need for complex hardware synchronization logic, as the system uses software-based dependency tracking to coordinate operand availability.
Solution Approach 2:
The patent changes the synchronization approach from fixed hardware delay lines to dynamic software-controlled synchronization. The compiler determines actual data dependencies at compile time and generates optimized synchronization instructions, allowing the system to adapt to variable instruction latencies without complex hardware control logic.
Data Source
AI summary
The technology disclosed provides a system that provides for compiling a dataflow graph to generate configuration data for a coarse-grained reconfigurable architecture (CGRA) having compute units, each with a pipeline of multiple stages including functional units and storage units. A compiler may receive a dataflow graph specifying data processing operations, allocate a particular stage of a particular compute unit to a particular data processing operation of the dataflow graph and determine that same-packet inputs consumed by the particular stage are unsynchronized due to a first delay between a first earlier-arriving same-packet input and a latest-arriving same-packet input. The compiler may then generate configuration data that configures the particular compute unit to synchronize the same-packet inputs by using a first subset of storage units to extend storage of the first earlier-arriving same-packet input for as many clock cycles as the first delay.