CGRA Memory Bank Mapping via Linear Transformation
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Solution Overview
Problem
Coarse-grained reconfigurable architecture (CGRA) systems face performance and energy efficiency issues due to inefficient memory access and resource management, as existing compilation technologies fail to effectively optimize memory mapping and parallelism, leading to conflicts and increased memory requirements.
Innovation Solution
A data storage method and device for CGRA that employs a disengaged and engaged mode for memory banks, using a linear transformation-based approach to generate continuous memory bank numbers and internal offset addresses, minimizing conflicts and filling elements to optimize memory access, thereby reducing memory requirements and improving data reading efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is distributed into different memory banks for parallel access, then memory access speed is improved, but memory conflicts increase and require more memory resources
Solution Approach 1:
The patent segments data into different memory banks based on access patterns. By dividing the memory space into multiple banks and distributing data according to specific segmentation rules, the system enables parallel access to different banks while reducing conflicts. This segmentation allows simultaneous read/write operations across multiple banks, improving memory access speed without proportionally increasing total memory resources.
Solution Approach 2:
The patent introduces a new dimension for data organization by using multi-dimensional mapping techniques. Instead of traditional linear memory allocation, data is mapped across multiple dimensions (bank index, offset, etc.), allowing more efficient utilization of memory banks. This dimensional approach enables better parallelism and reduces the total memory capacity needed to achieve high-speed access.
2Productivity
If compilation technology is adapted for CGRA architecture, then computing efficiency is improved, but system complexity increases
Solution Approach 1:
The patent changes key parameters in the compilation process to optimize for CGRA architecture. By adjusting parameters such as loop tiling size, parallelization degree, and memory access patterns, the compiler generates code that efficiently utilizes CGRA's reconfigurable resources. These parameter changes improve computing efficiency without requiring fundamental changes to the compiler architecture, thus limiting the increase in system complexity.
Solution Approach 2:
The patent introduces dynamic adaptation mechanisms in the compilation technology. The compiler dynamically adjusts compilation strategies based on the specific CGRA configuration and application characteristics. This dynamic approach allows the system to optimize computing efficiency for different workloads without requiring a completely different compilation framework, thereby controlling system complexity.
Data Source
AI summary
A data storage method includes: obtaining memory banks of arithmetic data; generating undetermined memory bank numbers of the memory banks sequentially; scanning storage dimensions of the arithmetic data to obtain the undetermined memory bank numbers, filling elements to make the undetermined memory bank numbers continuous if the undetermined memory bank numbers of two adjacent dimensions are not continuous; taking as a current transformation vector through a greedy algorithm a determined transformation vector where conflict is least and the number of the filling elements is smallest; generating current memory bank numbers of the memory banks according to the current transformation vector; converting each of the current memory bank numbers into a physical storage bank address through an offset function to obtain a corresponding internal offset address; and storing the arithmetic data into the memory banks according to the current memory bank numbers and the internal offset addresses.