Coarse-Grained Reconfigurable Array Memory Controller Segmentation
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Solution Overview
Problem
Existing coarse-grained reconfigurable array (CGRA) architectures face challenges in reducing execution time while maintaining simplicity, as complex architectures provide limited gains in execution time.
Innovation Solution
A CGRA architecture comprising a network of processing elements and memory units, connected for efficient data exchange, along with a compiler and memory controller to convert tasks into elementary operations and allocate instructions optimally for execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a data memory router is added between each processing unit to reduce memory access time, then execution time is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory access function by introducing dedicated memory controllers that separate data loading operations from processing operations. Each processing element has its own memory controller that manages data fetches independently, eliminating the need for complex routers while reducing memory access time through parallelized memory operations.
Solution Approach 2:
The patent implements preliminary action by having memory controllers fetch input data before processing operations are needed. The memory controller loads data into processing elements in advance, so when the processing element needs to execute an operation, the data is already ready, thereby reducing execution time without requiring complex real-time routing infrastructure.
2Device complexity
If data loading operations are integrated into processing elements, then device complexity is reduced, but execution time increases
Solution Approach 1:
The patent divides the system into two functional segments: processing elements that perform computations and memory controllers that handle data loading. This segmentation allows processing elements to remain simple while memory controllers specialize in efficient data fetches, achieving both low complexity and high performance.
Solution Approach 2:
The memory controller acts as an intermediary between the external memory and processing elements. It manages the data loading process independently, optimizing memory access patterns and preparing data before it is needed by processing elements, thereby reducing overall execution time without complicating the processing element architecture.
3Productivity
If multiple memory units are connected to processing elements, then data exchange efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory subsystem into multiple independent memory units, each connected to specific processing elements. This segmentation allows parallel data loading from different memory units simultaneously, improving data exchange efficiency while keeping each memory unit's connection structure simple and manageable.
Solution Approach 2:
Multiple memory units perform preliminary data loading operations in parallel before processing elements need data. The memory controllers coordinate these preliminary actions to fetch required data from different memory units simultaneously, improving productivity without creating complex interconnections between memory units themselves.
Data Source
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AI summary
The present invention concerns a coarse-grained reconfigurable array architecture (10) adapted to carry out tasks comprising: - a network (12) of processing elements (PE), - a network (14) of memory units (MU), - a compiler (18) converting the tasks to be carried out into elementary operations consisting in applying a calculation on input data to calculate an output data by executing input data exchange instruction, a calculation instruction and an output data exchange instruction, - a memory controller (20) fetching the input data exchange, calculation and output data exchange instructions, the memory controller (20) sending each calculation and output data exchange to the appropriate processing element (PE) to execute said instructions, and the memory controller (20) sending each input data exchange instruction to the appropriate memory unit (MU) to execute said instruction.