CGRA Quiesce Logic for Checkpointing and Multitasking
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Solution Overview
Problem
Checkpointing, multitasking, and multiprogramming in distributed processing systems, such as coarse-grain reconfigurable architectures (CGRAs), present complex issues as there is typically no capability to interrupt the machine during execution for system management functions like pre-emptive multitasking and debugging, necessitating an efficient means to manage quiesce of processing units.
Innovation Solution
A quiesce logic system is introduced, comprising logic circuits and a skew counter to track execution progress among processing units, allowing for synchronized quiesce at defined boundaries, enabling efficient quiesce of processing units in a CGRA by responding to control signals and managing quiesce boundaries across asynchronous operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processing units in a CGRA execute operations asynchronously to maximize operating efficiency, then productivity is improved, but it becomes difficult to coordinate quiesce among processing units and implement system management functions like checkpointing and multitasking
Solution Approach 1:
The patent segments the execution flow into distinct operations with defined boundaries, allowing the quiesce logic to independently manage synchronization at each boundary. This segmentation enables asynchronous execution within operations while maintaining coordination control at boundaries, resolving the contradiction between productivity and coordination complexity.
Solution Approach 2:
The quiesce logic acts as an intermediary between asynchronously executing processing units and the system management functions. It receives quiesce requests, coordinates with individual processing units to determine readiness, and manages the overall quiesce state, thereby enabling checkpointing and multitasking without disrupting asynchronous execution efficiency.
2Device complexity
If the runtime control program loads a configuration file and executes the machine to completion without interruption capability, then device complexity is reduced, but it loses the ability to implement pre-emptive multitasking, debugging, and other system management functions
Solution Approach 1:
The patent incorporates quiesce logic and synchronization boundaries into the configuration file structure beforehand. This preliminary design enables the system to support interruption, checkpointing, and multitasking capabilities while maintaining a relatively simple runtime control structure that loads and executes configurations with built-in quiesce support.
Solution Approach 2:
The quiesce logic provides multi-functionality by simultaneously supporting checkpointing, pre-emptive multitasking, debugging, and coordination of asynchronous operations. This universal mechanism enables diverse system management functions without requiring separate complex control structures for each function.
3Reliability
If the quiesce logic waits for all processing units to reach a quiesce boundary before quiescing, then reliability is improved by ensuring consistent state, but it increases the time required to quiesce the processing units
Solution Approach 1:
The quiesce logic employs feedback mechanisms by monitoring the state of processing units and receiving quiesce ready signals from each unit. This feedback enables the quiesce logic to determine when all units have reached appropriate quiesce boundaries, ensuring state consistency while providing the information needed to proceed with quiesce operations efficiently.
Data Source
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AI summary
A reconfigurable data processor comprises an array of configurable units configurable to allocate a plurality of sets of configurable units in the array to implement respective execution fragments of the data processing operation. Quiesce logic is coupled to configurable units in the array, configurable to respond to a quiesce control signal to quiesce the sets of configurable units in the array on quiesce boundaries of the respective execution fragments, and to forward quiesce ready signals for the respective execution fragments when the corresponding sets of processing units are ready. An array quiesce controller distributes the quiesce control signal to configurable units in the array, and receives quiesce ready signals for the respective execution fragments from the quiesce logic.