CGRA Scheduler Using Memory Variable Graphs for Tile Assignment
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Solution Overview
Problem
Traditional compilation tools face challenges in programming operations for new architectures like the streaming engine (SE) implemented using a coarse grained reconfigurable array (CGRA), requiring precise scheduling of instructions to maintain synchronous data flows and avoid corrupting operations.
Innovation Solution
An innovative assembly language is developed that describes programs as graphs representing data flows, allowing for the determination of a synchronous schedule and configuration of hardware details, with a corresponding parser and compiler to automate the conversion from high-level programming languages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional assembly language programming is used with virtual registers mapped to physical registers, then register reuse can be implemented, but the programming complexity and debugging difficulty increase significantly for new architectures like CGRA
Solution Approach 1:
The patent introduces an intermediary assembly language specifically designed for CGRA that acts as a mediator between high-level programming concepts and the underlying hardware architecture. This assembly language uses memory variable names instead of traditional register names, providing an abstract interface that simplifies programming while maintaining full control over the CGRA execution model. The intermediary layer handles the complexity of mapping to physical resources, allowing programmers to work with a simpler mental model.
Solution Approach 2:
The patent fundamentally changes the parameter representation from traditional register-based naming to memory variable-based naming. Instead of using virtual register names that must be mapped to physical registers, the system uses memory variable names that directly correspond to the CGRA's memory architecture. This parameter change simplifies the programming model by eliminating the need to understand and manage the virtual-to-physical register mapping complexity.
2Reliability
If precise scheduling of instructions is implemented to maintain synchronous data flows in CGRA, then execution correctness is ensured, but the scheduling complexity and time required increases
Solution Approach 1:
The patent implements preliminary action by performing instruction scheduling and configuration generation in advance, before execution. The toolchain analyzes the assembly language program, determines the optimal execution schedule for all instructions across multiple CGRA tiles, and generates the complete configuration beforehand. This pre-computation approach ensures execution correctness by validating the synchronous data flow schedule in advance, while reducing runtime overhead to minimal execution control.
Solution Approach 2:
The system employs self-service through automated toolchain components that independently handle scheduling, tile configuration, and resource allocation. The compiler and scheduler automatically analyze the program's data dependencies and generate the optimal execution schedule without requiring manual intervention. This automation reduces the time investment required from developers while ensuring correct synchronous execution through algorithmic optimization.
3Productivity
If assembly language programs are converted from high-level languages with automated toolchains, then programming speed increases, but the need for specialized parsers and compilers increases device complexity
Solution Approach 1:
The patent applies universality by designing the CGRA assembly language and toolchain to handle multiple functions within a unified framework. The same assembly language syntax and semantics are used across different CGRA configurations and tile types, allowing a single toolchain implementation to support various hardware instances. The parser and compiler are designed to be configuration-agnostic, processing assembly programs uniformly regardless of the specific target hardware, thereby reducing toolchain complexity while maintaining high programming productivity.
Data Source
AI summary
Schedule instructions of a program for execution on a coarse grained reconfigurable array having a plurality of tiles operable in parallel. The program identifies data flows through memory locations represented by memory variables and identifies instructions configured to transform data in the data flows. Based on a hardware profile identifying features of the coarse grained reconfigurable array, a scheduler is configured to generate a memory map. The memory map identifies, for each respective memory variable in the program, one of the tiles that contains a memory location represented by the respective memory variable. Based on the memory map reducing possible choices for a brute force search, the scheduler assigns the instructions to the tiles for execution, and determines timing of execution of the instructions in the tiles.