CGRA Stage Scheduling for Memory Mapping and Dataflow Throughput
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Solution Overview
Problem
Optimizing compute graphs for the configurable units of coarse-grained reconfigurable architectures (CGRAs) remains a challenge, particularly in managing memory mapping operations and dataflow synchronization for parallel and pipelined computations in machine learning and artificial intelligence workloads.
Innovation Solution
A method for reducing latency and increasing throughput in reconfigurable computing systems by converting user programs with tensor-based algebraic expressions into intermediate representations, analyzing critical stages, and moving memory mapping operations to adjacent stages executable by memory units, utilizing a grid of compute and memory units connected via a switching array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If memory mapping operations are performed within critical stages, then computation accuracy is maintained, but latency increases and throughput decreases
Solution Approach 1:
The patent applies preliminary action by moving memory mapping operations from critical stages to adjacent non-critical stages in advance. This allows the memory mapping to be completed before the critical stage execution, eliminating it from the critical path and thereby reducing latency and increasing throughput while maintaining computational correctness.
2Productivity
If memory mapping operations are moved to adjacent stages, then latency is reduced and throughput increases, but dataflow synchronization complexity increases
Solution Approach 1:
The patent uses buffers as intermediary elements between stages. These buffers act as mediators that handle dataflow synchronization automatically, absorbing the complexity of coordinating data transfer between stages while allowing memory mapping operations to be moved to non-critical stages. This enables throughput improvement without requiring complex synchronization logic to be manually managed.
3Productivity
If more memory units are allocated for parallel operations, then throughput increases, but device area increases
Solution Approach 1:
The patent applies dynamics by enabling reconfigurable memory units that can dynamically change their function and connectivity between different operational phases. This allows the same physical memory resources to be reused across multiple stages and operations, achieving high throughput through temporal parallelism rather than requiring proportional increases in physical memory capacity, thereby avoiding area expansion.
Data Source
AI summary
A method for generating configuration data configured to be executed by a reconfigurable dataflow computing system comprising an array of configurable units interconnected with a switching array. The method including receiving a user program comprising a plurality of expressions, converting the plurality of expressions to an intermediate representation comprising a plurality of stages, including a first stage and a second stage of the plurality of stages, each stage comprising one or more logical operations executable via dataflow through one or more configurable units of the array of configurable units, detecting a memory mapping operation within the first stage, and generating configuration data for the reconfigurable dataflow computing system based on the intermediate representation with the memory mapping operation moved to a second stage, wherein the configuration data, when loaded onto an instance of the reconfigurable dataflow computing system, causes the instance to implement at least the user program.