CGRA Design Space Exploration for Workload Mapping
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Solution Overview
Problem
Traditional compilation tools face challenges in programming operations for new architectures like the streaming engine implemented using a coarse grained reconfigurable array (CGRA), particularly in scheduling instructions to maintain the synchronous flow of data between tiles, which requires precise timing and correct tile alignment.
Innovation Solution
An assembly language is developed that describes programs as data flow graphs, allowing for the configuration of dispatch interfaces, memory interfaces, and tile memories, enabling a scheduler to generate an execution configuration that maps instructions to tiles with proper timing, using a software tool to automate the process and leverage reinforcement learning for efficient instruction placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional assembly language programming is used with virtual register mapping to physical registers, then register reuse can be achieved, but the programming complexity and time required increases significantly
Solution Approach 1:
The patent extracts the complex register allocation and timing management logic from the programmer's responsibility and relocates it to automated compilation tools. The compiler automatically handles virtual-to-physical register mapping, timing insertion, and resource allocation, allowing programmers to write high-level code without manually managing register reuse or timing constraints.
Solution Approach 2:
The patent introduces an intermediate representation layer between the high-level programming language and the low-level hardware instructions. This intermediate representation allows the compilation process to automatically optimize register allocation and timing without requiring the programmer to directly manage these details, thus reducing programming time while maintaining efficient resource utilization.
2Reliability
If manual configuration of CGRA is performed to ensure correct tile alignment and synchronous data flow, then execution correctness is achieved, but the effort and time required increases
Solution Approach 1:
The patent performs preliminary configuration of tile alignments, data flow paths, and synchronization timing during the compilation phase. The compiler analyzes the program's data dependencies and automatically generates the correct tile mappings and timing information before execution, eliminating the need for manual configuration while ensuring execution correctness.
Solution Approach 2:
The patent replaces manual mechanical configuration processes with automated software-based compilation and code generation. Instead of requiring programmers to manually configure tile alignments and data flow paths, the system uses intelligent algorithms to automatically generate the correct configuration, significantly reducing configuration time while maintaining reliability.
3Reliability
If precise timing and tile alignment are enforced for synchronous data flow in CGRA, then data flow correctness is maintained, but the device complexity increases
Solution Approach 1:
The patent creates a universal compilation framework that handles multiple aspects of CGRA configuration (tile mapping, timing insertion, data flow optimization, resource allocation) through a single integrated system. This universal approach consolidates what would otherwise require multiple separate configuration tools and processes, reducing overall system complexity while maintaining data flow correctness.
4Adaptability or versatility
If traditional compilation tools are used for new CGRA architecture, then existing tool compatibility is maintained, but programming efficiency and performance optimization decrease
Solution Approach 1:
The patent implements a dynamic compilation system that adapts to the specific characteristics of the CGRA architecture while maintaining compatibility with existing programming models. The compiler dynamically optimizes code generation based on the target hardware's features, such as tile configurations and data flow patterns, enabling both tool compatibility and improved programming efficiency.
Data Source
AI summary
An exploration tool of a design space of configurations to execute a data flow program using circuit tiles of a coarse grained reconfigurable array. The tool can identify different configurations for the program and determine performance metrics of the configurations. A user of the tool can provide one or more criteria in a request to the tool; and in response, the tool can identify, from the different configurations and based on the one or more criteria applied to the performance metrics, a first configuration of executing the program on the coarse grained reconfigurable array. For example, the tool can use a toolchain to generate the configurations and use a simulator to run simulations of executions of the program according to the configurations. The tool can compare attributes determined by the toolchain and the simulator for consistency in detecting errors or defects in the toolchain and the simulator.