Chain-Based TDM Logic Circuit for FPGA Resource Limits
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Solution Overview
Problem
Field Programmable Gate Arrays (FPGAs) face resource capacity limitations, making it difficult to implement large chip designs, and existing time-division multiplexing methods incur overhead and complexity in chip design verification processes.
Innovation Solution
A chain-based time-division multiplexing logic circuit is introduced, allowing computations to be performed sequentially through a single computation core, reducing resource requirements and simplifying the chip design implementation process in FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional time-division multiplexing is used to implement complex chip designs in FPGAs, then the chip design capacity can be increased, but the device complexity and overhead increase
Solution Approach 1:
The patent extracts the multiplexing control logic from the computation core and implements it through a simple chain-based structure. The computation core only performs computations while the chain structure handles data transmission and timing control, separating complex control functions from the computational unit to reduce overall system complexity.
Solution Approach 2:
The patent segments the time-division multiplexing function into discrete chain-based modules that can be independently configured. Each segment handles specific timing and data transmission tasks, allowing the system to achieve complex multiplexing functionality through simple, modular components rather than a monolithic complex controller.
2Productivity
If multiple computation cores are used to increase processing capacity, then the chip design can be implemented, but the resource capacity required increases
Solution Approach 1:
The patent implements a single computation core that performs multiple functions through time-division multiplexing. The same computation core executes different computations at different time slots, eliminating the need for multiple dedicated computation cores and reducing overall resource capacity requirements while maintaining high processing capacity.
Solution Approach 2:
The computation core operates in periodic cycles, executing computations sequentially at different time slots. This periodic operation allows a single core to handle multiple computation tasks that would traditionally require multiple simultaneous cores, reducing resource consumption while maintaining processing capacity.
3Reliability
If additional control mechanisms are added to manage time-division multiplexing, then the chip design can be verified, but the verification process overhead increases
Solution Approach 1:
The chain-based structure inherently provides timing control and data synchronization through its sequential architecture. The system self-manages the multiplexing process without requiring external control mechanisms, allowing the verification process to proceed more quickly since the timing and control aspects are built into the structure itself rather than requiring separate verification of control logic.
Data Source
AI summary
A processor includes a parallel-in serial-out (PISO) shift register, a combinational logic circuit, and a serial-in parallel-out (SIPO) shift register. The PISO shift register has a plurality of input ports configured to parallelly receive a plurality of electronic logic signals. The combinational logic circuit has a first input port connected to the output port of the PISO shift register and generates an electronic logic signal to be output to a first output port of the combinational logic circuit based on an electronic logic signal applied to the first input port of the combinational logic circuit. The SIPO shift register has an input port connected to the first output port of the combinational logic circuit. The SIPO shift register is configured to shift stored electronic logic signals with an electronic logic signal applied to the input port of the SIPO shift register and parallelly output stored electronic logic signals.