Chained Bus Memory Device Addressing

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Solution Overview

Problem

Existing configurations for coupling multiple memory devices to a host device, such as radial and multi-drop configurations, face issues like increased pin counts and bus contention, leading to signal integrity problems and complexity in addressing multiple devices.

Innovation Solution

A chained bus memory configuration where memory devices are connected in a chain with a single data output and input port on the host, allowing point-to-point signaling and simplifying the addressing process by using default identifiers and registers to detect and assign unique identifiers to each device in the chain.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If radial configuration is used to couple multiple memory devices, then all memory devices can be connected to the host, but the pin count required increases significantly

Engineering Contradiction:

Improvenumber of memory devices connectedVSAvoidpin count

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system segments the memory device connections into individual chain segments, where each memory device connects to only one predecessor and one successor device. This segmentation allows multiple memory devices to be connected through a single host interface, eliminating the need for multiple pins per device while maintaining full connectivity.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If multi-drop or multi-bus configurations are used to connect multiple memory devices, then connection complexity is reduced, but bus contention and signal integrity problems occur

Engineering Contradiction:

Improveconnection configurationVSAvoidsignal integrity

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

Instead of having multiple devices share a common bus (multi-drop), the invention inverts the approach by creating point-to-point connections in a chain where each device has dedicated communication paths with its immediate neighbors. This eliminates bus contention while maintaining connection simplicity.

Inventive Principle:

Principle #13The other way round (Inversion)

3Device complexity

If chained bus configuration is used to reduce pin count, then addressing multiple devices becomes complex

Engineering Contradiction:

Improvepin countVSAvoidaddressing process

Core Design Contradiction:

Device complexityVSEase of operation

Solution Approach 1:

Each memory device in the chain autonomously determines its position and address by listening for address signals from the host and propagating them through the chain. Devices automatically identify themselves and their positions without requiring complex external addressing circuitry, enabling the system to self-configure and self-address.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS10664411B2Chained bus memory device

Publication Date: 2020.05.26 MICRON TECHNOLOGY INC

AI summary

Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.