Chained Memory ECC Architecture for Faster Write and Recovery
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Solution Overview
Problem
Existing memory configurations, such as RAID and Chipkill architectures, face performance bottlenecks during write operations and error recovery due to the need to update error correcting code data, leading to slower write speeds and complex recovery processes.
Innovation Solution
The proposed memory configuration employs a chain-based architecture with dual or single paths and an error check and correcting unit, allowing data to be recovered efficiently by using XOR operations and redundant data paths, which reduces the memory needed for error recovery information and enhances operating speed during write operations and error recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RAID configurations are used to protect data with error correcting code, then data reliability is improved, but write operation speed deteriorates because two writes are required for every operation
Solution Approach 1:
The memory system is segmented into multiple independent chains, each capable of autonomous error correction. By dividing the memory into chains where each chain has its own ECC unit, the system can perform error correction locally without requiring coordinated writes across all memory devices, thus improving write speed while maintaining reliability.
Solution Approach 2:
Error correcting code data is pre-calculated and stored in dedicated ECC memory units within each chain before actual memory operations occur. This preliminary preparation of correction data eliminates the need for additional write operations during normal memory writes, as the ECC data is already positioned and ready for rapid error correction.
2Reliability
If RAID configurations are used with error correcting code, then data reliability is improved, but error recovery speed deteriorates because all disks must be read individually
Solution Approach 1:
The memory recovery process is segmented into independent chain-level operations. When an error occurs in one chain, only that specific chain needs to be accessed for recovery, while other chains continue operating normally. This segmentation of the recovery process into independent units dramatically reduces the time required for error recovery compared to reading all disks individually.
Solution Approach 2:
Dedicated ECC memory units act as intermediaries that store pre-calculated correction data within each chain. During error recovery, these intermediary ECC units provide the necessary correction data locally, eliminating the need to read through all memory devices to reconstruct corrected data, thus accelerating the recovery process.
3Reliability
If Chipkill architecture scatters error correcting code bits across multiple memory chips, then single chip failure protection is improved, but device complexity increases
Solution Approach 1:
The memory system is divided into discrete chains, each with its own dedicated ECC unit and correction logic. This segmentation isolates the complexity within manageable chain-level units rather than requiring system-wide complex coordination, making the overall architecture more maintainable and easier to implement while preserving single chip failure protection capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves write performance and reduces latency during error recovery by allowing simultaneous data flow in both directions, enabling full recovery from most path and memory unit errors while doubling available bandwidth.
Implementation Method 1
allowing data to be recovered efficiently by using XOR operations and redundant data paths
Data Source
AI summary
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units. The chain can include an error check and correcting unit (ECC). Additional apparatus, systems, and methods are disclosed.