Chained Memory Devices for Error Recovery
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Solution Overview
Problem
Current memory configurations require significant additional memory and slow down performance during write operations due to the need for error correction and recovery, especially in high-density integrated circuits and RAID systems, and often necessitate different components or increased costs depending on ECC requirements.
Innovation Solution
A chained memory configuration where error recovery data is calculated as the sum of data across multiple memory devices, allowing for efficient error correction and recovery without additional components or performance impact, using a serially interconnected system with an ECC device at the end of the chain to reconstruct data in case of failures, and enabling ECC inclusion or exclusion without added expense.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RAID configurations are used for error recovery, then data protection against multiple drive failures is improved, but write operation speed deteriorates to approximately one half the performance of reading
Solution Approach 1:
The memory system is segmented into multiple independent memory devices arranged in a chain, where each device handles a portion of the data. This segmentation allows parallel processing of different data portions while maintaining error recovery capabilities, thus improving write speed without sacrificing reliability.
Solution Approach 2:
Error recovery data is calculated and stored in advance as the sum of data across multiple memory devices. When a failure occurs, the recovery data is already prepared and can be immediately used to reconstruct lost information, eliminating the need for slow recovery calculations during failure events.
2Reliability
If ECC data is stored in separate memory locations for error correction, then error correction capability is improved, but the amount of memory required increases
Solution Approach 1:
Data and error correction data are merged into a single memory device. The error correction data is stored in the same memory device that holds the original data, eliminating the need for separate dedicated ECC memory locations and thus reducing the total memory capacity required.
Solution Approach 2:
Each memory device in the chain serves multiple functions: storing original data, storing error correction data for that data, and participating in the calculation of recovery data. This multi-functionality reduces the overall memory requirements while maintaining comprehensive error correction capability.
3Reliability
If ChipkillTM configuration is used to protect against single memory chip failure, then reliability against chip failure is improved, but additional memory area and chip area are required
Solution Approach 1:
The memory chain performs self-diagnosis and self-recovery. Each memory device contributes to the error correction data for the others, and the system can automatically detect and correct failures without external intervention. This self-service capability provides chip failure protection without requiring additional dedicated correction memory area.
4Device complexity
If simpler detection/correction schemes such as parity check are implemented, then device complexity is reduced, but error correction capability is limited
Solution Approach 1:
Error correction data acts as an intermediary between the original data and the error correction process. This intermediary contains the sum of multiple data portions and enables complex error correction and recovery capabilities while keeping the actual correction logic relatively simple, as it only requires basic summation operations.
Data Source
AI summary
Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain. In one configuration shown, the serial chain of memory devices includes a chain of devices where each device is a stacked die memory device. Methods are described that show using the error recovery device in write operations and data recovery operations.