Chained Packet Commands for Low-Latency Accelerator Processing
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Solution Overview
Problem
Programmable logic devices face increased latency and bandwidth consumption due to multiple round trip communications with the processor or programmable fabric device when performing multiple operations on packets, which is inefficient for packet processing.
Innovation Solution
Implementing a chained command architecture that allows multiple operations to be performed using a single command, reducing the need for multiple communications and memory accesses by chaining accelerator engines in stages, thus optimizing latency and bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple operations are performed on a packet using multiple round trip communications with the processor or programmable fabric device, then the packet can undergo multiple processing steps, but the latency increases and bandwidth consumption increases
Solution Approach 1:
The IPU divides the packet processing operations into multiple independent accelerator engines (e.g., CRC engine, crypto engine, checksum engine) arranged in parallel stages. Each engine can process different packets simultaneously, eliminating the sequential dependency that causes latency in traditional multi-round-trip approaches.
Solution Approach 2:
The IPU acts as an intermediary between the processor/programmable fabric and the accelerator engines. It receives a single command from the processor, distributes it to multiple accelerator engines for parallel processing, and aggregates the results, thereby reducing multiple round-trip communications to a single round-trip communication.
2Productivity
If multiple operations are performed on a packet using multiple round trip communications, then comprehensive processing is achieved, but memory bandwidth consumption increases
Solution Approach 1:
The packet processing function is segmented across multiple accelerator engines within the IPU. Each engine processes a specific aspect of the packet (e.g., CRC calculation, encryption, checksum) independently and in parallel, eliminating the need for repeated memory accesses that would occur with sequential processing rounds.
Solution Approach 2:
Multiple accelerator engines are merged into a single integrated IPU unit that can execute multiple operations on a packet simultaneously. This consolidation allows the IPU to perform comprehensive packet processing in a single operation cycle, dramatically reducing memory bandwidth consumption compared to multiple separate operations.
3Adaptability or versatility
If multiple accelerator engines are used for packet processing, then processing flexibility is improved, but communication overhead with the processor increases
Solution Approach 1:
The IPU is designed as a universal processing unit that can execute multiple types of packet processing operations through a single command interface. The same IPU can dynamically configure different accelerator engines to handle various protocols, encryption algorithms, and processing requirements, providing flexibility without increasing communication complexity.
Data Source
AI summary
Systems or methods of the present disclosure may include a programmable logic device having a first portion of programmable elements configured to implement a user logic. The programmable logic device also includes a second portion of the programmable elements. The second portion is configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines. The IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.