Chained Resource Locking for Compute-Near-Memory Parallel Efficiency
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Solution Overview
Problem
Current computer architectures face inefficiencies in data transfer between processors and memory, leading to performance and capacity constraints, particularly in compute-intensive operations like neural networks and simulations, due to high cache miss rates and traditional locking mechanisms that limit parallel execution efficiency.
Innovation Solution
The implementation of a compute-near-memory (CNM) system with hybrid threading processors and a scalable locking mechanism that uses event messaging to pass locks between threads, eliminating contention on lock values and improving parallel efficiency by allowing threads to initiate their own threads or sub-threads, thereby reducing latency and enhancing system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional locking mechanisms are used for resource management, then thread synchronization is achieved, but parallel execution efficiency deteriorates due to lock contention
Solution Approach 1:
The patent introduces an event messaging system as an intermediary between threads that need synchronized access to shared resources. Instead of threads directly contending for locks, they post events to a queue and receive notifications when resources become available. This mediator approach eliminates direct lock contention while maintaining synchronization guarantees, allowing multiple threads to proceed in parallel without blocking each other.
2Adaptability or versatility
If compute units are placed far from memory, then memory access flexibility is improved, but data transfer time and energy consumption increase
Solution Approach 1:
The patent segments the computing system into multiple compute-near-memory units, each with its own local memory and processing elements. This segmentation allows data to be processed close to where it is stored, eliminating the need for frequent long-distance data transfers. Each segment can independently access its local memory without interfering with other segments, maintaining flexibility while reducing transfer time and energy consumption.
3Productivity
If cache memory size is increased to reduce cache misses, then compute-intensive operation performance improves, but memory capacity and cost increase
Solution Approach 1:
The patent transitions from a traditional hierarchical memory model to a compute-near-memory architecture where processing elements are distributed across multiple memory modules. This dimensional change allows the system to achieve high performance for compute-intensive operations by placing compute units close to memory, eliminating the need for large cache memory while maintaining low latency access to data.
Data Source
AI summary
Devices and techniques for chained resource locking are described herein. Threads form a last-in-first-out (LIFO) queue on a resource lock to create a chained lock on the resource. A data store representing the lock for the resource holds the previous thread's identifier, enabling a subsequent thread to wake the previous thread using the identifier when the subsequent thread releases the lock. Generally, the thread releasing the lock need not interact with the data store, reducing contention for the data store among many threads.