Chained Sequencer Circuitry for Precise Power Transition Timing

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Solution Overview

Problem

Conventional sequencers have a limited number of output channels, which cannot meet the sequencing requirements of modern electronic systems, and employing multiple sequencers leads to issues with maintaining strict timing during power transitions.

Innovation Solution

The implementation of sequencer chaining circuitry that connects separate sequencers in a feed-forward and/or feed-backward manner to ensure proper timing during sequencing, allowing for the scaling of sequencer output requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple separate sequencers are employed to provide required quantity of output channels, then the quantity of output channels is increased, but maintaining strict timing during sequencing becomes problematic

Engineering Contradiction:
Improvequantity of output channelsVSAvoidtiming precision
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent combines multiple sequencers into a unified chained architecture where sequencer output signals are fed forward to subsequent sequencers and fed backward to previous sequencers. This merging approach allows multiple sequencers to operate as an integrated system, maintaining strict timing relationships across all output channels while providing a large quantity of sequenced outputs.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements feedback connections where output signals from each sequencer are fed backward to previous sequencers in the chain. This feedback mechanism ensures that timing requirements are maintained across all sequencers by allowing each sequencer to synchronize its operation with the overall system timing, thus resolving the timing precision problem when using multiple sequencers.

Inventive Principle:
Principle #23Feedback

2Device complexity

If conventional sequencers with limited output channels are used, then device complexity is reduced, but sequencing requirements of modern electronic systems cannot be met

Engineering Contradiction:
Improvesequencer configuration simplicityVSAvoidsequencing capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent segments the sequencing function into multiple independent sequencer units that can be chained together. Each sequencer unit maintains a manageable level of complexity individually, but when chained together they provide the versatility and quantity of output channels needed for modern electronic systems. This segmentation allows the system to scale without proportionally increasing individual component complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates a universal sequencer chaining architecture that can be configured to meet various sequencing requirements. The chained sequencer system provides multi-functionality by able to generate a large number of sequenced output channels while maintaining a relatively simple base unit design, thus achieving both adaptability and controlled complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4085460B1Sequencer chaining circuitry
Publication Date: 2025.08.13 MICRON TECHNOLOGY INC
  • EP4085460B1 patent drawingFigure 1
  • EP4085460B1 patent drawingFigure 2
  • EP4085460B1 patent drawingFigure 3

AI summary

A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.