Low-Dimensional Source-Drain Barrier for Contact Resistance Reduction
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Solution Overview
Problem
Current semiconductor device manufacturing faces challenges in integrating low dimensional materials effectively, particularly in achieving low contact resistance and reducing parasitic capacitance.
Innovation Solution
The integration of a barrier layer made of a second low dimensional material, which is in contact with a semiconductor layer made of a first low dimensional material, to form a source/drain structure. This barrier layer is formed through a chalcogen treatment of a pre-layer, ensuring a low contact resistance and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional materials and structures are used for source/drain regions, then manufacturing is straightforward, but contact resistance is high and parasitic capacitance is increased
Solution Approach 1:
The patent changes the material parameters by using low dimensional materials (2D materials like TMDs, graphene) instead of conventional 3D materials for source/drain regions. This parameter change in material dimensionality reduces both contact resistance and parasitic capacitance while maintaining manufacturability through established semiconductor processing techniques
Solution Approach 2:
The patent employs composite material structures combining different low dimensional materials (e.g., TMD semiconductor layer with graphene contact regions) to achieve optimal electrical properties. The composite approach allows tailoring contact resistance and capacitance characteristics by selecting materials with complementary properties
2Reliability
If conventional source/drain structures are used, then device fabrication is simpler, but parasitic capacitance is high
Solution Approach 1:
The patent reduces parasitic capacitance by changing the vertical dimension parameter - using atomically thin 2D materials instead of thick 3D materials. This dimensional parameter change directly reduces the overlap capacitance between source/drain regions and gate, improving device performance
Solution Approach 2:
The patent introduces low dimensional barrier layers and interface engineering as intermediaries between metal contacts and semiconductor channels. These intermediary layers optimize the electrical interface, reducing contact resistance without significantly increasing parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces contact resistance and parasitic capacitance, enhancing the performance of semiconductor devices by utilizing low dimensional materials effectively.
Implementation Method 1
This barrier layer is formed through a chalcogen treatment of a pre-layer
Data Source
AI summary
A semiconductor device including a substrate, a semiconductor layer, a gate, a dielectric structure, and a source/drain structure is provided. The semiconductor layer is disposed on the substrate, and is made of a first low dimensional material. The gate is disposed on the substrate and overlaps the semiconductor layer. The dielectric structure is disposed on the semiconductor layer and includes a trench structure reaching a portion of the semiconductor layer. The source/drain structure includes a barrier layer made of a second low dimensional material continuously extending along the trench structure and a metal fill filling a volume surrounded by the barrier layer.