Chalcogen Layer Composition Gradient for Phase Change Memory
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Solution Overview
Problem
The miniaturization of semiconductor storage devices is hindered by the reduction in the width of the chalcogen layer, which affects the voltage difference between high and low resistance states, leading to a decrease in the reliability of memory cell electrical characteristics due to element movement and biased composition ratios during repeated energization.
Innovation Solution
The chalcogen layer's composition ratio of germanium, antimony, and tellurium is optimized by increasing the ratio of tellurium from the anode side to the cathode side and decreasing the ratio of germanium and antimony, achieved through film-formation methods like Physical Vapor Deposition or Chemical Vapor Deposition, to maintain a uniform distribution and enhance the phase change region ratio, thereby maintaining the voltage difference and reducing the chalcogen layer width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the chalcogen layer width is reduced to enable miniaturization, then the device size is reduced, but the voltage difference between high and low resistance states decreases
Solution Approach 1:
The patent applies local quality by creating a non-uniform composition distribution within the chalcogen layer. Specifically, the ratio of Ge and Sb atoms is made smaller near the anode side while the ratio of Te atoms is made larger near the anode side, creating localized compositional variations that optimize phase change properties and maintain voltage difference even in reduced-width layers
Solution Approach 2:
The patent changes the compositional parameters of the chalcogen layer by controlling the ratios of Ge, Sb, and Te atoms through film formation processes. By adjusting these atomic ratios and creating gradient distributions, the patent maintains the electrical characteristics and voltage difference necessary for reliable operation while enabling miniaturization
2Volume of moving object
If the chalcogen layer width is reduced, then the device can be miniaturized, but element movement and biased composition ratios occur during repeated energization
Solution Approach 1:
The patent creates localized compositional regions within the chalcogen layer where Ge and Sb concentrations are lower and Te concentrations are higher near the anode side. This local quality variation prevents uniform element migration and composition biasing that would otherwise occur during repeated energization cycles
Solution Approach 2:
The patent performs preliminary compositional optimization during the film formation process by establishing the desired non-uniform atomic ratio distribution before operation. This preliminary action of creating the gradient structure prevents element movement and composition biasing during subsequent repeated energization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reduction of the chalcogen layer width while preserving the voltage difference between high and low resistance states, ensuring stable memory cell performance and preventing a decrease in electrical characteristics.
Implementation Method 1
the chalcogen layer has a phase change region in which a ratio of a Ge atom, an Sb atom, and a Te atom is increased or decreased from the anode side toward the cathode side
Implementation Method 2
achieved through film-formation methods like Physical Vapor Deposition or Chemical Vapor Deposition
Implementation Method 3
achieved through film-formation methods like Physical Vapor Deposition or Chemical Vapor Deposition
Data Source
AI summary
A semiconductor storage device includes a first conductive layer, a second conductive layer, and a first chalcogen layer provided therebetween. A third conductive layer and a fourth conductive layer have a second chalcogen layer provided therebetween. The second chalcogen layer contains tellurium (Te). When a minimum value and a maximum value of a composition ratio of tellurium in the second chalcogen layer observed along the first direction are a first minimum value and a first maximum value, respectively, the first minimum value is observed at a position closer to the third conductive layer than a center position in the first direction of the second chalcogen layer, and the first maximum value is observed at a position closer to the fourth conductive layer than the center position in the first direction of the second chalcogen layer.