Transition Metal Chalcogenide Barrier Layers for Semiconductor Interconnects

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Solution Overview

Problem

Current interconnect technologies face challenges in scaling down due to the thickness limitations of barrier layers, which increase resistance and hinder the deposition of uniform transition metal chalcogenide layers compatible with back-end of line (BEOL) processing, especially for very thin transition metal chalcogenide layers required in semiconductor devices.

Innovation Solution

A method involving the deposition of transition metal chalcogenide barrier layers using a transition metal precursor and a reactive chalcogen species in a reaction chamber, employing atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes, with plasma enhancement to achieve thin, uniform layers of 3 nm or less, utilizing metal organic precursors and controlling plasma parameters for effective chemisorption and self-limiting reactions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a thicker TaN barrier layer is deposited using PVD to prevent Cu diffusion, then diffusion protection is improved, but the space for filling via/trench with Cu is reduced and resistance increases

Engineering Contradiction:
Improvediffusion protectionVSAvoidbarrier layer thickness control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the material composition parameter from conventional TaN to transition metal chalcogenides (such as MoS2, WS2, WSe2), which enable effective barrier protection at thicknesses of 3 nm or less, resolving the contradiction between sufficient barrier thickness for diffusion protection and thin enough thickness to allow adequate Cu filling space

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the PVD deposition mechanism with ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition) processes, which provide superior thickness control and uniformity, enabling precise deposition of ultra-thin barrier layers with atomic-level precision

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If the barrier layer thickness is reduced to allow more Cu filling space, then resistance is reduced, but the barrier effectiveness against Cu diffusion deteriorates

Engineering Contradiction:
Improvevia/trench filling spaceVSAvoidbarrier effectiveness
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent employs transition metal chalcogenide materials (such as MoS2, WS2, WSe2) which possess unique two-dimensional layered structures with high barrier effectiveness per unit thickness, enabling ultra-thin layers of 3 nm or less to provide sufficient diffusion protection while maximizing Cu filling space

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent utilizes the anisotropic properties of 2D transition metal chalcogenide materials, where the layered structure provides exceptional barrier properties in the vertical direction (perpendicular to the layer) while maintaining thin overall thickness, achieving local optimization of barrier effectiveness

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If novel 2D materials are used to create thin barrier layers, then uniformity and thickness control are improved, but compatibility with BEOL processing conditions becomes challenging

Engineering Contradiction:
Improvelayer uniformityVSAvoidBEOL processing compatibility
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent optimizes deposition parameters including temperature, pressure, and precursor selection in ALD/CVD processes to achieve uniform 2D material deposition at temperatures compatible with BEOL processing, resolving the contradiction between layer uniformity and processing compatibility

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the deposition of thin, uniform transition metal chalcogenide barrier layers that effectively prevent metal diffusion, reducing resistance and enhancing the scalability of semiconductor interconnects by maintaining the functionality of semiconductor devices with minimal thermal budget and complex surface morphology handling.

Implementation Method 1

employing atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes, with plasma enhancement to achieve thin, uniform layers of 3 nm or less, utilizing metal organic precursors and controlling plasma parameters for effective chemisorption and self-limiting reactions

Methodology Applied
Scientific EffectChemisorption: Chemisorption

Implementation Method 2

employing atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes, with plasma enhancement to achieve thin, uniform layers of 3 nm or less

Methodology Applied
Scientific EffectPlasma enhanced chemical vapor deposition: Plasma Enhanced Chemical Vapour Deposition

Data Source

PatentUS20220384197A1Method of depositing material and semiconductor devices
Publication Date: 2022.12.01 ASM IP HLDG BV
  • US20220384197A1 patent drawing
  • US20220384197A1 patent drawing
  • US20220384197A1 patent drawing

AI summary

The current disclosure relates to deposition of a transition metal chalcogenide barrier layer. The method of depositing a transition metal chalcogenide barrier layer comprises providing a substrate having an opening into a reaction chamber, providing a transition metal precursor in the reaction chamber in vapor phase and providing an reactive chalcogen species in the reaction chamber. The method may be a plasma-enhanced atomic layer deposition method. The disclosure further relates to an interconnect comprising a transition metal chalcogenide barrier layer.