2D Chalcogenide Bridge Channel with Graded Chalcogenization
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Solution Overview
Problem
Two-dimensional semiconductor materials face challenges in compatibility with existing silicon-based structures and processes, limiting their performance improvement due to material characteristics.
Innovation Solution
A semiconductor device is developed using a two-dimensional chalcogenide material, where a chalcogen element is implanted into a semiconductor material layer, allowing for the formation of a bridge pattern with specific chalcogenization portions overlapping gate structures and spacers, enhancing performance and compatibility with commercial processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two-dimensional semiconductor materials are used to improve mobility and short channel effect, then device performance is improved, but compatibility with existing silicon-based structures and processes deteriorates
Solution Approach 1:
The patent applies local quality by creating different chalcogenization portions with different chalcogen element concentrations at different locations within the bridge pattern. The first chalcogenization portion overlapping the gate structure has a higher chalcogen element concentration to enhance mobility and short channel effect suppression, while the second chalcogenization portion overlapping the gate spacer has a lower concentration to maintain compatibility with existing silicon-based processes and structures.
Solution Approach 2:
The patent utilizes parameter changes by varying the concentration of the chalcogen element between different portions of the bridge pattern. This allows optimization of device performance in the channel region while maintaining process compatibility in other regions, effectively resolving the contradiction between performance improvement and compatibility.
2Reliability
If chalcogen element concentration is increased to enhance mobility improvement, then carrier mobility is improved, but material stability and compatibility deteriorate
Solution Approach 1:
The patent applies local quality by concentrating the chalcogen element in specific regions (first chalcogenization portion overlapping the gate structure) where mobility enhancement is most needed, while maintaining lower concentrations in other regions (second chalcogenization portion overlapping the gate spacer) to preserve material stability and compatibility with existing processes.
Solution Approach 2:
The patent utilizes parameter changes by spatially varying the chalcogen element concentration parameter throughout the bridge pattern, allowing simultaneous optimization of carrier mobility in the channel region and material stability in regions interfacing with gate spacers and existing silicon-based structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enables the creation of semiconductor devices with improved performance by utilizing two-dimensional chalcogenide materials, addressing compatibility issues and enhancing mobility and short channel effect suppression.
Implementation Method 1
a chalcogen element is implanted into a semiconductor material layer
Data Source
AI summary
A semiconductor device including a substrate, a first bridge pattern spaced apart from the substrate and extending in a first direction and including a two-dimensional chalcogenide in which a semiconductor element and a chalcogen element are combined, a gate structure extending in a second direction intersecting the first direction and through which the first bridge pattern penetrates, a gate spacer extending along a side surface of the gate structure and through which the first bridge pattern penetrates and a source/drain pattern connected to the first bridge pattern on a side surface of the gate spacer, wherein the first bridge pattern includes a first chalcogenization portion overlapping the gate structure and a second chalcogenization portion overlapping the gate spacer, and a concentration of the chalcogen element in the second chalcogenization portion is lower than a concentration of the chalcogen element in the first chalcogenization portion, may be provided.