Chalcogenide Passivated III-V Interface for Low Defect Dielectric Integration
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Solution Overview
Problem
Current methods for passivating the interface between dielectric materials and III-V compounds in MOSFETs face challenges such as high interface state density, Fermi level pinning, and leakage issues, limiting the integration options and device performance.
Innovation Solution
A method involving the formation of a chalcogenide passivated surface by applying a thermal treatment to a substrate with a second III-V compound, followed by exposure to a chalcogenide hydride gas, to create a low defect interface suitable for high-κ dielectric deposition, which includes steps like surface reconstruction and dielectric layer formation under ultra-high-vacuum conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional passivation techniques (chalcogenide surface treatment, amorphous Si/Ge layers) are used to reduce interface state density, then interface quality improves, but Fermi level pinning persists and integration options are limited
Solution Approach 1:
The patent applies preliminary surface reconstruction treatment to the III-V compound surface before dielectric deposition. By performing thermal treatment in ultra-high-vacuum to create a group III element-rich surface, the method prepares the surface in advance to prevent Fermi level pinning and reduce interface states, enabling subsequent successful dielectric integration
Solution Approach 2:
The patent changes the surface composition parameter by creating a group III element-rich surface through thermal treatment. This parameter change transforms the surface from its native state to a controlled composition state that is compatible with high-κ dielectric materials, resolving the Fermi level pinning issue while maintaining low interface state density
2Stability of the object's composition
If specific passivation layers (GaGdOx, amorphous Si) are deposited to stabilize surface reconstruction, then interface stress is minimized, but integration flexibility is reduced and leakage issues occur
Solution Approach 1:
The patent extracts the specific requirement for particular passivation layer compositions (GaGdOx, amorphous Si) and replaces them with a more universal approach. By creating a group III element-rich surface through thermal treatment, the method removes the need for material-specific passivation layers, thereby increasing integration flexibility while maintaining surface stability
Solution Approach 2:
The patent creates a universal surface preparation method that works with various high-κ dielectric materials (Al2O3, HfO2, DyScO3) without requiring material-specific passivation layers. The group III element-rich surface serves as a universal interface that stabilizes reconstruction and enables diverse dielectric integrations, enhancing adaptability
3Manufacturing precision
If amorphous silicon layer is deposited on III-V substrate, then interface passivation is achieved, but stress control is lost and electron-counting for Fermi level pinning cannot be governed
Solution Approach 1:
The patent replaces the mechanical/amorphous silicon-based passivation approach with a thermal/chemical surface treatment method. By using ultra-high-vacuum thermal treatment to create a group III element-rich surface, the method substitutes complex stress-control mechanisms with a simpler thermal process that inherently provides both passivation and stress management
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces interface state density and Fermi level pinning, enabling improved device performance by forming a stable, low-defect interface that supports high-κ dielectric integration without the limitations of previous methods.
Implementation Method 1
applying a thermal treatment in ultra-high-vacuum to the substrate such that upon reaching a first temperature (T1) a surface reconstruction of the second III-V compound takes place, thereby forming a group III element-rich surface
Implementation Method 2
bringing the substrate containing the group III element-rich surface to a second temperature (T2) and subjecting the group III element-rich surface to an ambient comprising a chalcogenide hydride gas, thereby forming a chalcogenide passivated surface
Data Source
AI summary
The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.