Chamfered Semiconductor Die Corners for Dense Chiplet Packaging

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving denser die placement and improved electrical performance in packaging techniques, particularly in package-on-package (PoP) technology, where traditional methods struggle to efficiently integrate thermal management and mechanical bracing while maintaining small footprints and high integration density.

Innovation Solution

The implementation of chamfered edges or corners on semiconductor dies allows for denser die placement and the integration of thermal modules with mechanical braces, utilizing a redistribution structure with multiple layers for enhanced routing and enabling a chiplet design approach, which reduces chip-to-chip spacing and improves electrical performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional packaging methods are used, then manufacturing simplicity is maintained, but integration density and component density are insufficient

Engineering Contradiction:

Improveintegration densityVSAvoidpackaging structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements package-on-package (PoP) technology where a top semiconductor package is stacked on top of a bottom semiconductor package, creating a nested vertical arrangement that dramatically increases integration density and component density within a small footprint area

Inventive Principle:

Principle #7Nested doll (Nesting)

2Productivity

If die placement density is increased, then integration density improves, but thermal management becomes more difficult

Engineering Contradiction:

Improvedie placement densityVSAvoidthermal management

Core Design Contradiction:

ProductivityVSTemperature

Solution Approach 1:

The patent transitions from planar thermal management to three-dimensional thermal management by stacking packages vertically and integrating thermal modules in the vertical dimension, allowing heat dissipation paths to extend through multiple layers and levels

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Productivity

If chip-to-chip spacing is reduced, then integration density improves, but mechanical integrity and thermal module attachment become challenging

Engineering Contradiction:

Improvechip-to-chip spacingVSAvoidmechanical integrity

Core Design Contradiction:

ProductivityVSStrength

Solution Approach 1:

The patent employs asymmetric chamfered corners on semiconductor dies with different chamfer configurations (e.g., 45-degree angles on specific corners) that create asymmetric spacing patterns, allowing mechanical braces and thermal modules to be positioned in the asymmetric gaps while maintaining dense overall die placement

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS11854986B2Chamfered die of semiconductor package and method for forming the same

Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.