Chamfered Die Corners to Prevent Singulation Collision Damage

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing damage to integrated circuit dies during transportation due to collisions with adjacent inactive features, which can occur during the singulation process, leading to manufacturing yield and reliability issues.

Innovation Solution

The implementation of chamfered corners on both integrated circuit dies and inactive features creates an enlarged space between them, reducing the likelihood of collisions and stress during handling and packaging processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional singulation process is used without chamfered corners, then manufacturing process is simpler, but integrated circuit dies are more prone to collision damage with inactive features

Engineering Contradiction:
Improvedamage resistance of integrated circuit diesVSAvoidsingulation process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming chamfered corners on inactive features before the singulation process. This pre-prepared structural feature creates enlarged spaces that prevent collision damage to integrated circuit dies during subsequent handling and packaging operations, thereby improving reliability without adding complexity to the main singulation process.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If chamfered corners are formed on inactive features, then collision damage to integrated circuit dies is reduced, but manufacturing process steps increase

Engineering Contradiction:
Improvemanufacturing yieldVSAvoidmanufacturing process simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the formation of chamfered corners into the existing inactive feature fabrication process. By integrating this protective structural modification into the standard manufacturing flow, the patent improves manufacturing yield through reduced collision damage while minimizing the increase in process steps, as the chamfered corners are formed concurrently with other feature fabrication activities.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If standard singulation without enlarged spaces is used, then manufacturing process is faster, but stress concentration occurs during handling

Engineering Contradiction:
Improvesingulation process speedVSAvoidstress resistance of integrated circuit dies
Core Design Contradiction:
ProductivityVSStrength

Solution Approach 1:

The patent applies preliminary action by pre-forming chamfered corners that create enlarged spaces before the singulation and handling processes. This advance preparation prevents stress concentration during subsequent operations, improving the strength and stress resistance of integrated circuit dies without requiring additional time during the critical singulation process itself, thereby maintaining productivity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20240222292A1Method for Sigulating Semiconductor Devices and Package Device Including the Semiconductor Devices
Publication Date: 2024.07.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240222292A1 patent drawing
  • US20240222292A1 patent drawing
  • US20240222292A1 patent drawing

AI summary

In an embodiment, a device includes an integrated circuit die including a first sidewall, a second sidewall, and a third sidewall, wherein the third sidewall of the integrated circuit die is connected to the first sidewall of the integrated circuit die and the second sidewall of the integrated circuit die, wherein the third sidewall of the integrated circuit die forms a chamfered corner of the integrated circuit die; a first dielectric surrounding the integrated circuit die; a semiconductor feature disposed over the integrated circuit die, wherein the semiconductor feature includes a first sidewall, a second sidewall, and a third sidewall, wherein the third sidewall of the semiconductor feature is connected to the first sidewall of the semiconductor feature and the second sidewall of the semiconductor feature and forms a chamfered corner of the semiconductor feature; and a second dielectric surrounding the semiconductor feature.