Chamfered Insulating Fences for Semiconductor Integration Density
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Solution Overview
Problem
The increasing complexity of semiconductor device fabrication due to reduced process margins in lithography processes hinders the achievement of highly integrated semiconductor devices, necessitating innovative solutions for electrical isolation and integration density.
Innovation Solution
A semiconductor device design featuring line patterns with insulating fences having chamfered corners and elongated elliptical shapes, along with insulating patterns that fill gaps between the line patterns and fences, providing electrical isolation without exposing air gaps to the outside, thus enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lithography processes are used with reduced process margins, then manufacturing complexity increases, but integration density cannot be sufficiently improved
Solution Approach 1:
The fabrication process is divided into multiple etching stages with different selectivities. First, insulating fences are formed with initial corners. Then, corners are selectively chamfered using etching with specific selectivity ratios. Finally, insulating patterns are formed to fill the chamfered corners. This segmentation allows each step to be optimized independently, achieving high integration density without excessive overall process complexity.
Solution Approach 2:
The patent utilizes etching selectivity parameter changes between different material layers. By controlling the selectivity ratio between insulating fence material and line pattern material, and between insulating fence material and sacrificial pattern material, the process achieves precise dimensional control. This parameter control enables formation of chamfered corners with specific geometries that improve electrical isolation while maintaining compatibility with existing lithography processes.
2Reliability
If insulating fences with sharp corners are used, then electrical isolation is achieved, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The patent intentionally creates asymmetric corner geometry through chamfering. Instead of maintaining symmetric sharp corners, the corners are modified to have specific asymmetric shapes with controlled dimensions. This asymmetric design provides better process window and reduced sensitivity to fabrication variations, improving manufacturing precision while maintaining electrical isolation functionality.
Solution Approach 2:
The insulating fences are formed with preliminary corner structures before the final insulating patterns are deposited. The chamfering process is performed as a preliminary action to prepare the corner geometry. This preliminary shaping ensures that subsequent processes work with pre-optimized geometries, reducing variability in final dimensions and improving manufacturing precision.
3Ease of manufacture
If air gaps are exposed in the insulating structure, then manufacturing is simplified, but electrical reliability deteriorates
Solution Approach 1:
The patent applies different structural qualities to different regions of the insulating structure. In regions where electrical isolation is critical (at corners and interfaces between conductive patterns), solid insulating material is provided without air gaps. In other regions, the structure can be more open. This local differentiation maintains electrical reliability where needed while simplifying manufacturing in less critical areas.
Solution Approach 2:
The patent converts the potential harm of air gaps by strategically placing solid insulating material to seal critical regions. The chamfered corner design creates specific geometries where insulating patterns naturally fill and seal potential air gap formation zones. This approach maintains manufacturing simplicity while eliminating the reliability issues that exposed air gaps would cause in critical electrical isolation regions.
Data Source
AI summary
A semiconductor device includes line patterns disposed on a substrate, the line patterns extending in a first direction and being parallel to one another. The semiconductor device includes conductive patterns spaced apart from each other in the first direction between an adjacent pair of the line patterns. The semiconductor device includes insulating fences electrically isolating the conductive patterns from each other and having chamfered corners. The semiconductor device includes insulating patterns filling gaps between side surfaces of the line patterns and the chamfered corners of the insulating fences.