Chamfered VIA Mitigates TDDB in BEOL Interconnects
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Solution Overview
Problem
As the pitch between interconnects and wiring features in IC devices decreases, the likelihood of Time-Dependent Dielectric Breakdown (TDDB) of dielectric materials increases, leading to electrical shorts and other reliability issues.
Innovation Solution
The implementation of a chamfered Vertical Interconnect Access (VIA) with a vertical sidewall and a chamfered surface that exposes a portion of the lower wiring line, surrounded by a dielectric film layer and a sacrificial plug, which is removed to re-expose the wiring line while retaining the dielectric film layer, thereby increasing the dielectric material between interconnects and mitigating TDDB effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pitch between interconnects and wiring features is decreased to increase integration density, then the likelihood of TDDB of dielectric material increases, leading to electrical shorts and reliability issues
Solution Approach 1:
A chamfered surface is formed at the bottom of the VIA trench before filling it with conductive material. This preliminary geometric modification increases the surface area and distributes the electrical stress, preventing TDDB from the outset. The chamfered surface is created using selective etching processes that prepare the trench geometry in advance of the metal deposition step.
Solution Approach 2:
The VIA structure is modified locally at the trench bottom with a chamfered surface, while the upper portions maintain vertical sidewalls. This localized geometric change concentrates the stress-mitigation effect where it is most needed (at the high-stress interface with the lower wiring level) without compromising the overall VIA connectivity function.
2Reliability
If additional dielectric material is added to mitigate TDDB, then the reliability improves, but the capacitance between interconnects increases
Solution Approach 1:
The chamfered surface introduces a curved/angled geometry at the VIA bottom instead of a sharp 90-degree corner. This curved transition distributes the electric field more uniformly, reducing field concentration and TDDB risk without requiring additional dielectric material volume, thereby avoiding increased capacitance.
Solution Approach 2:
The solution addresses the TDDB problem by modifying the geometry in the lateral dimension (creating the chamfered angle) rather than simply adding more dielectric material in the vertical dimension. This dimensional approach reduces stress concentration through geometric distribution rather than material accumulation.
Data Source
AI summary
An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.