Chamfering Shift Register Circuit for GOA Gate Potential Control
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Solution Overview
Problem
In display technology, particularly in LCD and OLED displays, gate driver on array (GOA) circuits face challenges in preventing abrupt changes in gate potential, leading to poor display quality and increased costs.
Innovation Solution
A shift register circuit with an input sub-circuit, output sub-circuit, and chamfering sub-circuit is designed to manage potential changes, allowing the potential of a node to jump from an initial to a higher potential, then gradually decrease, and finally return to the initial potential, thereby preventing direct jumps in output signals and ensuring a chamfered output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional shift register circuit is used, then the circuit structure is simple, but the output signal exhibits abrupt jumps from high to low levels causing poor display quality
Solution Approach 1:
The shift register circuit is divided into three functional sub-circuits: input sub-circuit, output sub-circuit, and chamfering sub-circuit. Each sub-circuit performs a specific function in the signal processing chain, allowing the abrupt output jump to be segmented into controlled potential changes followed by gradual chamfering degradation.
Solution Approach 2:
The chamfering sub-circuit acts as an intermediary between the input and output sub-circuits. It receives the clock signal and node potential from the input sub-circuit, processes them through multiple transistors to generate a gradual potential degradation, and outputs the chamfered signal to the output sub-circuit, thereby mediating the abrupt transition.
2Reliability
If the gate potential changes abruptly, then the circuit operation is fast, but the display quality deteriorates due to direct jumps in output signals
Solution Approach 1:
The chamfering sub-circuit introduces a periodic action by using the clock signal to control the gradual degradation of node potential through multiple transistor stages. Instead of a single abrupt change, the potential degrades in a controlled sequence during the clock cycle, creating a chamfered waveform that improves display quality while maintaining timing precision.
Data Source
AI summary
A shift register circuit includes: an input sub-circuit connected to a first node, and configured to receive a first control signal, and cause a potential of the first node to jump from an initial potential to a first potential greater than the initial potential; an output sub-circuit connected to the first node, and configured to receive a first clock signal, generate an output signal, cause the potential of the first node to jump from the first potential to a third potential greater than the first potential; and a chamfering sub-circuit connected to the first node, and configured to receive a second control signal, cause the potential of the first node to gradually decrease from the third potential to a fourth potential greater than the initial potential and less than the third potential, and cause the potential of the first node to jump from the fourth potential to the initial potential.