Chamferless Via Formation Using Etch Stop Layer
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Solution Overview
Problem
The dual damascene process for forming interconnects in integrated circuits often results in enlarged chamfers during trench etching, leading to via shorts and increased time-dependent dielectric breakdown due to overlay errors, non-uniformity, and liner erosion, particularly at the wafer edge during dielectric reactive ion etching.
Innovation Solution
A method involving a slower etch rate interlayer dielectric etch stop layer between two interlayer dielectric layers, using aluminum oxynitride as the etch stop layer, to form a chamferless via structure, which extends through the etch stop layer, allowing precise control of via and wire trench openings during dual damascene processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench etching is performed during dual damascene processing to create wire trench openings, then wire interconnection is achieved, but enlarged chamfers are created that can cause via shorts
Solution Approach 1:
The patent applies preliminary action by forming the via opening through the etch stop layer before performing the trench etching operation. The etch stop layer is deposited and patterned to define the via opening boundaries in advance, protecting the via profile from subsequent trench etching processes. This sequential approach ensures the via opening is established with precise dimensions before any trench formation occurs.
Solution Approach 2:
The etch stop layer serves as an intermediary element between the via opening definition and the trench etching process. This intermediate layer with controlled etch selectivity allows the via opening to be defined and protected while enabling subsequent trench formation. The etch stop layer acts as a buffer that prevents the trench etching from directly impacting the via opening profile, thereby maintaining via integrity.
2Reliability
If overlay error occurs in mask patterning for via and wire, then manufacturing variability increases, but via shorts are more likely to occur due to enlarged chamfer
Solution Approach 1:
The etch stop layer acts as an intermediary that decouples the via opening definition from the trench etching process. By defining the via opening through the etch stop layer with its own dedicated patterning step, the via dimensions are determined independently of subsequent trench formation. This intermediary layer absorbs overlay variations, preventing them from directly causing via shorts.
Solution Approach 2:
The via opening is preliminarily defined through the etch stop layer before trench etching occurs. This preliminary definition establishes the via boundaries with precise control, and any subsequent overlay errors during trench formation do not affect the already-defined via opening. The preliminary action ensures via integrity regardless of later alignment variations.
3Reliability
If trench etching is performed after via etching, then wire trench openings are created, but via bumpout occurs that can short via to wire above
Solution Approach 1:
The etch stop layer serves as a protective intermediary between the via opening and the subsequent trench etching process. When trenches are etched through the dielectric layers, the etch stop layer prevents lateral erosion from creating via bumpouts that would connect to overlying wires. This intermediary layer maintains the via profile integrity throughout the trench formation process.
Solution Approach 2:
The via opening is preliminarily formed and protected by the etch stop layer before any trench etching takes place. This preliminary via formation with protective coverage ensures that subsequent trench formation cannot create harmful bumpouts. The preliminary action establishes a protected via structure that remains isolated from trenches even as they are formed nearby.
4Reliability
If etch stop layer erosion occurs during dielectric reactive ion etching at wafer edge, then process non-uniformity increases, but via profile control deteriorates
Solution Approach 1:
The patent changes the material parameter of the etch stop layer to have significantly different etch selectivity compared to surrounding dielectric layers. This parameter change ensures that the etch stop layer resists erosion during reactive ion etching processes, maintaining via profile uniformity even at wafer edges where process non-uniformity is typically more severe. The selective etch resistance compensates for edge effects.
Solution Approach 2:
The etch stop layer acts as an intermediary that protects the via opening from lateral erosion during dielectric reactive ion etching. Even when process non-uniformity causes increased erosion in other layers at the wafer edge, the etch stop layer maintains its integrity and continues to define the via profile accurately. This intermediary protection ensures consistent via formation across the entire wafer surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents via shorts and enhances reliability by maintaining a chamferless via profile, reducing time-dependent dielectric breakdown, and improving overlay process control, thereby increasing the reliability and capacitance of interconnects.
Implementation Method 1
the occurrence of shorts can still be increased because of the increased chances of time dependent dielectric breakdown (TDDB) caused by the overlay error or liner erosion
Data Source
AI summary
Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.