Chamferless Via Etching with Removable Sealant Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Challenges arise in semiconductor device fabrication as devices shrink, leading to the formation of chamfers at via-trench junctions, which can cause reliability issues and reduce the minimum insulator distance between adjacent vias, resulting in potential short circuits and leakage.
Innovation Solution
The integration of a conformal removable sealant layer, such as Group IV metal-containing oxides or nitrides, is used to protect the ultra-low k dielectric material during etching, preventing chamfer formation by acting as a sacrificial layer that can be removed without damaging the underlying material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching of ULK dielectric material is performed to form via and trench structures, then the via and trench structures are formed, but chamfers are created at the corners leading to reduced insulator thickness and reliability issues
Solution Approach 1:
A conformal removable sealant layer is deposited as an intermediary protective layer between the etching process and the ULK dielectric material corners. This sealant layer prevents direct contact between the etching chemistry and the corners, thereby preventing chamfer formation while allowing the via and trench structures to be formed. The sealant layer is subsequently removed after serving its protective function.
Solution Approach 2:
The conformal removable sealant layer is deposited in advance before the etching process to pre-protect the corners of the ULK dielectric material. This preliminary protective action ensures that when the etching chemistry is introduced, the corners are already shielded, preventing chamfer formation from occurring in the first place.
2Productivity
If harsher etching chemistries are used to improve etching performance, then etching speed and via/trench formation are improved, but the ULK dielectric material corners are damaged causing chamfer formation
Solution Approach 1:
The conformal removable sealant layer serves as a mediator that allows harsh etching chemistries to be used for improved etching speed while preventing these same chemistries from damaging the corners. The sealant layer absorbs the aggressive chemistry, protecting the underlying ULK dielectric material corners from chamfer formation.
Solution Approach 2:
The conformal removable sealant layer provides beforehand cushioning protection to the corners against the harmful effects of harsh etching chemistries. By depositing this protective layer prior to etching, the corners are cushioned against the aggressive chemistry, allowing high-speed etching without corner damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of vias with vertical sidewalls, maintaining structural integrity and reducing reliability issues by minimizing chamfers, thus enhancing device performance and yield.
Implementation Method 1
The use of a conformal removable sealant layer, such as tin oxide or tin nitride, deposited between the trench and via levels, acts as a protective layer to prevent corner erosion during etching
Implementation Method 2
a conformal removable sealant layer, such as tin oxide or tin nitride, deposited between the trench and via levels
Data Source
AI summary
Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.


