Change-Sensing Flip-Flop for Near-Threshold Stable Data Capture
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Solution Overview
Problem
Existing flip-flops in digital systems operating in near-threshold voltage regions are vulnerable to process variations and instability due to the lack of a fully static, contention-free, and no redundant clock transition condition, especially when input data frequency exceeds clock frequency.
Innovation Solution
A static change-sensing flip-flop design incorporating a master latch, slave latch, pull-up and pull-down network complementary circuits, and a change-sensing circuit to prevent wrong data output and eliminate redundant clock transitions, ensuring fully static and contention-free operation even when input data frequency exceeds clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the system operating voltage is reduced to near-threshold voltage region to solve power issues, then power consumption is reduced, but sequential logic elements become vulnerable to process variation and system operation stability increases
Solution Approach 1:
The flip-flop is divided into master latch and slave latch sections, each with dedicated pull-up and pull-down networks. This segmentation allows independent optimization of each section's static characteristics, ensuring stable operation at near-threshold voltages while maintaining low power consumption.
Solution Approach 2:
Complementary pull-up and pull-down networks are pre-configured in both master and slave latches to prevent floating nodes and ensure deterministic switching behavior. This beforehand preparation of balanced networks cushions against process variations and maintains reliability at reduced voltages.
2Reliability
If verification is performed only when clock frequency is faster than input data frequency, then fully static and contention-free characteristics are verified, but instability in flip-flop operation may be discovered when input data frequency is faster than clock frequency
Solution Approach 1:
Pull-up and pull-down networks are designed to be active and balanced under all input conditions, including when input data frequency exceeds clock frequency. This beforehand cushioning ensures stable operation across all verification scenarios without requiring separate optimization for each condition.
Solution Approach 2:
The circuit parameters of pull-up and pull-down networks are optimized to maintain balanced drive strengths across varying frequency conditions. This parameter optimization ensures the flip-flop maintains its fully static and contention-free characteristics regardless of the relationship between input data and clock frequencies.
3Use of energy by moving object
If redundant clock transitions are eliminated using change-sensing scheme, then power consumption and operating speed are improved, but wrong data output may occur in pull-up or pull-down network operations
Solution Approach 1:
Complementary circuits act as intermediary verification mechanisms that monitor the state of discharge nodes and prevent wrong data output. These intermediary circuits detect and correct potential errors before they propagate, ensuring data correctness while maintaining the power savings from eliminated redundant clock transitions.
Solution Approach 2:
The pull-up and pull-down networks incorporate feedback mechanisms that monitor their own operation state and prevent wrong data output. This feedback ensures that change-sensing operations correctly update the flip-flop state only when valid transitions occur, maintaining reliability while reducing power consumption.
Data Source
AI summary
Provided is a static change-sensing flip-flop. The static change-sensing flip-flop proposed herein includes a master latch and a slave latch configured to transfer and maintain input data according to a clock, and the master latch includes a pull-up network complementary circuit configured to connect to a master latch node (DN) and to prevent output of wrong data in a pull-up network operation while operating according to input data (D); a pull-down network complementary circuit configured to connect to the master latch node (DN) and to prevent output of wrong data in a pull-down network operation while operating according to a clock (CK); and a change-sensing circuit configured to prevent output of wrong data by a clock node (CS) and the master latch node (DN) in the pull-down network operation of the master latch.