Semiconductor Die Layout With Channel Above Field Electrode Trench
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Solution Overview
Problem
Existing vertical transistor designs face limitations in further reducing lateral dimensions due to the required width of the field electrode trench, which affects conductivity and breakdown robustness, and also impede channel length reduction.
Innovation Solution
A semiconductor die design with a lateral channel region vertically aligned above a field electrode trench, allowing for efficient area use and simplified channel length reduction, incorporating a field electrode trench with a lateral gate region and vertical channel alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertical field electrode trench is used with lateral gate and channel regions, then area utilization is improved, but the lateral dimensions cannot be reduced further due to the required width of the field electrode trench
Solution Approach 1:
The patent transitions from a conventional lateral arrangement of gate and channel regions to a vertical arrangement where the channel region is positioned directly above the field electrode trench. This dimensional change allows the gate region to extend laterally over the trench, effectively utilizing the vertical space above the trench structure and reducing the lateral footprint of the device.
Solution Approach 2:
The gate region is positioned to overhang the field electrode trench, with the channel region nested above the trench structure. This nesting arrangement allows the gate to span across the trench width without requiring additional lateral space, as the trench structure serves as a support for the overhanging gate region.
2Area of stationary object
If the field electrode trench width is reduced to shrink pitch, then area use is improved, but conductivity and breakdown robustness of the field electrode deteriorate
Solution Approach 1:
The gate region is designed with non-uniform thickness, being thicker at the edges and thinner in the center above the trench. This local quality variation allows the gate edges to provide structural support and maintain field electrode stability, while the thinner central region reduces overall capacitance. The field electrode trench width can be reduced without compromising reliability because the thicker gate edges locally reinforce the structure.
Solution Approach 2:
The patent changes the geometric parameters of the gate region, specifically introducing a thickness gradient across the gate. This parameter change allows the gate to maintain mechanical and electrical stability over a narrower trench while reducing the trench width for pitch shrink. The varying thickness parameter enables the gate to perform multiple functions: providing structural support at the edges and reducing capacitance in the center.
3Speed
If the channel length is reduced to improve device performance, then speed is improved, but the body doping profile becomes difficult to control in vertical designs
Solution Approach 1:
By positioning the channel region vertically above the field electrode trench rather than laterally adjacent to it, the patent enables independent control of channel length and trench width. The channel length can be reduced in the vertical dimension without being constrained by the lateral trench width, allowing for shorter channel lengths that improve device speed while maintaining proper doping profiles through standard fabrication processes.
Data Source
AI summary
The disclosure relates to a semiconductor die with a transistor device, having a source region, a drain region, a body region including a channel region, a gate region, which includes a gate electrode, next to the channel region, for controlling a channel formation, a drift region between the channel region and the drain region, and a field electrode region with a field electrode formed in a field electrode trench, which extends into the drift region, wherein the channel region extends laterally and is aligned vertically with the gate region, and wherein at least a portion of the channel region is arranged vertically above the field electrode region.