Channel Local Contact Etching Stop Structure for Gate-Line Protection

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Solution Overview

Problem

In semiconductor manufacturing, the etching process for forming channel local contacts and other structures poses a risk of damaging adjacent gate-line structures due to insufficient etching window margins and the use of the same etching stop material, leading to electrical performance issues and reduced yield rates.

Innovation Solution

A semiconductor device design where a first dielectric layer with different insulating material is used as an etching stop layer, covering the gate-line structure, and a channel local contact is formed on this layer, reducing the impact of etching on the gate-line structure by setting a reasonable etching selection ratio between the two materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the same etching stop material is used for both the etching stop layer and isolation structures, then the manufacturing process is simplified, but the etching window margin becomes insufficient causing damage to gate-line structures

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidetching window margin
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by using different etching stop materials for different structures: silicon nitride for the etching stop layer and silicon oxide for isolation structures. This material differentiation creates distinct etching rates and selectivity, allowing precise control of the etching process to protect gate-line structures while maintaining manufacturing feasibility

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the material parameter of the etching stop layer from silicon oxide to silicon nitride, which has different etching characteristics. This parameter change creates a larger etching window margin by establishing better etching selectivity between the stop layer and surrounding materials, thereby preventing damage to gate-line structures

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a sufficient etching window margin is maintained to protect gate-line structures, then damage to isolation structures is reduced, but the etching process becomes more complex and time-consuming

Engineering Contradiction:
Improvegate-line structure integrityVSAvoidetching process efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By changing the etching stop layer material to silicon nitride, the patent achieves higher etching selectivity, which naturally provides a larger process window. This allows the etching process to proceed more efficiently without requiring excessive margin adjustments, thus maintaining both reliability and productivity

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If different insulating materials are used for the first dielectric layer and contact layer, then etching selectivity is improved reducing damage, but the device structure becomes more complex

Engineering Contradiction:
Improveetching selectivityVSAvoiddielectric layer structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements local quality by assigning different materials (silicon nitride for first dielectric layer, silicon oxide for contact layer) to different functional regions. This localized material differentiation improves etching selectivity precisely where needed while keeping the overall device structure manageable through targeted complexity

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250015156A1Semiconductor device and preparation method thereof
Publication Date: 2025.01.09 YANGTZE MEMORY TECH CO LTD
  • US20250015156A1 patent drawing
  • US20250015156A1 patent drawing
  • US20250015156A1 patent drawing

AI summary

According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stacked layer and a top select gate layer located on the stacked layer. The semiconductor device may include a gate-line structure extending through the top select gate layer and the stacked layer. A portion of the gate-line structure that extends through the top select gate layer may be a first isolation structure, and the first isolation structure may include a contact layer in contact with the top select gate layer. The semiconductor device may include a channel structure extending through the stacked layer and a first dielectric layer located on the top select gate layer, where the first dielectric layer and the contact layer comprise different insulating materials. The semiconductor device may include a channel local contact extending through the first dielectric layer and corresponding to the channel structure.