Channel Control Circuit for Semiconductor Test Efficiency
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Solution Overview
Problem
Current semiconductor devices face limitations in test efficiency, particularly in the direct access mode, where it is impossible to perform boundary tests on individual channels, control electrical fuses of each channel, or measure current by channel, due to the need for common signal application across all channels.
Innovation Solution
A channel control circuit that generates specific control signals to selectively activate and deactivate channels, allowing for independent operation of one channel while maintaining a structural connection for simultaneous testing across multiple channels, enabling various tests to be performed on each channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct access mode is used to test all channels simultaneously, then testing coverage is improved, but individual channel control capability deteriorates
Solution Approach 1:
The patent divides the control of multiple channels into independent controllable units. Each channel can be individually activated or deactivated through separate control signals while maintaining the ability to test all channels simultaneously. This segmentation allows granular control over each channel's test state without compromising overall testing coverage.
Solution Approach 2:
The patent implements dynamic channel activation and deactivation capabilities. The control circuit can change the operational state of each channel in real-time during testing, allowing the system to transition between testing individual channels and testing all channels simultaneously based on test requirements.
2Device complexity
If common signal application is used for all channels, then structural simplicity is maintained, but boundary test capability deteriorates
Solution Approach 1:
The control circuit segments the common signal application into channel-specific control paths. While a common signal structure is maintained, separate control signals are generated for each channel based on the test mode, enabling boundary tests for individual channels without significantly increasing structural complexity.
Solution Approach 2:
The control circuit acts as an intermediary between the common signal application and individual channel requirements. It receives common test signals and translates them into channel-specific control signals, enabling boundary testing while maintaining the simplicity of common signal application architecture.
3Productivity
If all channels are tested simultaneously, then test time is reduced, but individual channel measurement capability deteriorates
Solution Approach 1:
The patent enables dynamic switching between parallel testing of all channels and sequential testing of individual channels. The control circuit can activate specific channels for detailed measurement while deactivating others, allowing individual channel current measurement and other precise measurements without permanently sacrificing the ability to test all channels simultaneously.
Solution Approach 2:
The control circuit implements periodic activation and deactivation of channels during the test sequence. Channels are activated in specific periods for individual measurement, then deactivated and reactivated for parallel testing, creating a periodic pattern that accommodates both individual measurement and overall productivity requirements.
4Ease of operation
If direct access mode is used, then ease of testing is improved, but electrical fuse control capability deteriorates
Solution Approach 1:
The control circuit segments the electrical fuse control into channel-specific control paths. Each channel has its own control signal that can independently activate or deactivate the electrical fuse for that channel, enabling selective current path control while maintaining the ease of testing through the same control mechanism.
Data Source
AI summary
A channel control circuit having a plurality of channels according to an embodiment of the present invention includes: a channel control signal generating block configured to generate a channel control signal capable of selectively controlling an activated state of a channel in response to a combination of a first test mode signal and a second test mode signal; a scan buffer control signal generating block configured to generate a scan buffer control signal in response to the first test mode signal and a scan signal; a clock buffer control signal generating block configured to generate a clock buffer control signal in response to the channel control signal and the scan buffer control signal; and a clock input buffer configured to generate a clock output signal, which is used as an internal clock of a semiconductor device, in response to the clock buffer control signal.