Channel Controller Bulk Invalidate Cache Coherency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current cache invalidate methods in computing systems are inefficient, particularly when performing bit vector operations, as they often require flushing entire cache lines or marking pages as uncacheable, which consumes significant power and time, and making a Processor-in-Memory (PIM) device fully cache coherency protocol aware is costly and complex.
Innovation Solution
The implementation of a memory device with sensing circuitry and a channel controller that allows for bulk invalidate commands to be sent to a cache memory system, enabling efficient interaction between a bit vector operation memory device and a cache-based memory system by invalidating specific cache entries, reducing the need for costly flushing operations and maintaining cache coherency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache invalidate methods are used to maintain cache coherency during bit vector operations, then cache coherency is maintained, but power consumption and processing time increase significantly due to flushing entire cache lines or marking pages as uncacheable
Solution Approach 1:
The patent segments the cache invalidation process by introducing a separate invalidation buffer that stores invalidation commands independently from the main cache operations. This allows specific cache entries to be invalidated selectively rather than flushing entire cache lines, reducing unnecessary power consumption while maintaining cache coherency for bit vector operations
Solution Approach 2:
The patent introduces an invalidation buffer as an intermediary component between the cache memory system and the processing units. This buffer mediates invalidation commands, allowing the system to track and invalidate specific cache entries without triggering full cache line flushes, thereby reducing power consumption while preserving cache coherency
2Reliability
If traditional cache invalidate methods are used to maintain cache coherency during bit vector operations, then cache coherency is maintained, but processing time increases due to costly flushing operations
Solution Approach 1:
By segmenting the invalidation process into discrete commands stored in the invalidation buffer, the system can invalidate only the specific cache entries that need to be invalidated for bit vector operations, rather than flushing entire cache lines. This selective approach significantly reduces processing time while maintaining cache coherency
Solution Approach 2:
The invalidation buffer pre-stores invalidation commands before they are executed, allowing the system to prepare and queue invalidation operations in advance. This preliminary action reduces the critical path delay during bit vector operations by decoupling the invalidation command generation from the actual cache invalidation execution
3Reliability
If a PIM device is made fully cache coherency protocol aware to maintain cache coherency, then cache coherency is maintained, but device complexity and cost increase significantly
Solution Approach 1:
The invalidation buffer serves as an intermediary that simplifies the PIM device architecture by handling cache invalidation commands externally. The PIM device does not need to be fully cache coherency protocol aware, as the invalidation buffer manages the coherency requirements, thereby reducing device complexity and cost while maintaining cache coherency
Solution Approach 2:
The patent extracts the cache coherency management functionality from the PIM device itself and places it in the external invalidation buffer. This separation allows the PIM device to focus on bit vector operations without the complexity of implementing full cache coherency protocols, reducing architectural complexity while maintaining coherency through the external buffer
4Reliability
If entire cache lines are flushed to maintain cache coherency during bit vector operations, then cache coherency is maintained, but bandwidth consumption increases due to unnecessary memory accesses
Solution Approach 1:
The invalidation buffer enables segmentation of cache invalidation at the entry level rather than at the cache line level. This allows the system to invalidate only the specific cache entries that contain data relevant to bit vector operations, avoiding unnecessary memory accesses and reducing bandwidth consumption while maintaining cache coherency
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.