Channel Convolution Engine for AI Workloads
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Solution Overview
Problem
Existing hardware solutions struggle to efficiently compute convolution operations for complex artificial intelligence problems, particularly depthwise convolutions, due to complexity and resource constraints, necessitating a more efficient hardware platform that optimizes performance without increasing complexity.
Innovation Solution
A processor system with a channel convolution processor unit that performs convolution operations using vector units for efficient matrix operations, where data and weight matrices are processed in parallel, and reuse of data elements across iterations to minimize reloading and enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional optimization approaches for depthwise convolution are used, then convolution performance is improved, but hardware complexity and memory organization complexity increase significantly
Solution Approach 1:
The patent implements a universal convolution engine that can perform multiple types of convolution operations (standard convolution, depthwise convolution, pointwise convolution) using the same hardware infrastructure. The engine uses a unified data layout (NHWC format) and consistent processing pipeline to handle different convolution types without requiring specialized hardware for each operation type, thereby improving productivity while avoiding excessive complexity
Solution Approach 2:
The patent segments the convolution computation into distinct stages: data loading, filtering, and result accumulation. Each stage is handled by dedicated functional units within the convolution engine, allowing for efficient parallel processing while maintaining modular architecture that avoids overall system complexity
2Speed
If specialized hardware is used for depthwise convolution, then computation speed is improved, but hardware compatibility for different matrix operations is reduced
Solution Approach 1:
The convolution engine is designed as a universal platform that can execute multiple matrix operations including standard convolution, depthwise convolution, and pointwise convolution. The engine uses configurable parameters (such as group count and kernel size) to adapt to different operation types without requiring specialized hardware, thus maintaining speed improvement while ensuring broad compatibility
Solution Approach 2:
The patent employs dynamic configuration of the convolution engine parameters to accommodate different matrix operations. The engine can dynamically adjust its behavior based on the operation type being performed, allowing it to optimize for speed in depthwise convolution while remaining compatible with other matrix operations through parameter reconfiguration
Data Source
AI summary
A processor system comprises a first and second group of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate convolution weight matrix for each channel. Each register stores at least one data element from each convolution weight matrix. The hardware channel convolution processor unit is configured to multiply each data element in the first group of registers with a corresponding data element in the second group of registers and sum together the multiplication results for each specific channel to determine corresponding channel convolution result data elements in a corresponding channel convolution result matrix.