Channel Decoder for SSD Memory Port Selection
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Solution Overview
Problem
Conventional solid state drives experience delays in memory channel selection due to the need for command transmission from hardware logic to the microcontroller unit and subsequent control signal processing through GPIO pins, which negatively impacts random read/write performance.
Innovation Solution
The implementation of a channel decoder that decodes a selection signal to directly select memory ports and output ports, bypassing the general purpose input/output control pin, allowing for faster memory access and improved performance by using flash memory signals to control channel selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If GPIO pin control is used for channel selection, then the system has simple control structure, but channel selection delay increases
Solution Approach 1:
The patent extracts the channel selection control function from the general-purpose MCU GPIO system and creates a dedicated hardware control path. The channel decoder receives control signals directly from memory control logic, bypassing the MCU firmware and GPIO pins, thereby eliminating the delay associated with the original control structure while maintaining system manageability.
Solution Approach 2:
The patent introduces a channel decoder as an intermediary component between the memory control logic and the memory channels. This intermediary hardware component translates control signals directly to channel selection, creating a dedicated fast path that mediates between the control logic and multiple memory channels without involving the general-purpose GPIO system.
2Productivity
If MCU firmware control is used for channel selection, then the system has centralized control, but random read/write performance deteriorates
Solution Approach 1:
The patent replaces the software-based MCU firmware control mechanism with a hardware-based channel decoder. This substitution eliminates the sequential processing delays inherent in firmware execution and GPIO signal processing, enabling parallel or near-parallel channel selection operations that directly improve random read/write performance while maintaining centralized control through hardware logic.
3Speed
If hardware logic sends command to MCU, then the system has modular architecture, but channel selection speed decreases
Solution Approach 1:
The patent extracts the channel selection decision-making function from the MCU and implements it directly in hardware logic. The channel decoder is controlled by memory control logic that operates independently of the MCU, creating a parallel control path that eliminates the command transmission delay while preserving the modular architecture through clear separation of control functions.
Data Source
AI summary
An apparatus comprising a first circuit, a second circuit and a channel decoder. The first circuit may comprise (i) a controller port and (ii) a plurality of memory ports. The second circuit may comprise (i) input port and (ii) a plurality of output ports. The channel decoder may be configured to decode a selection signal. The channel decoder may be configured to select (i) one of the plurality of memory ports and (ii) one of the plurality of output ports in response to the decoded selection signal. The selection signal may be received by the controller port and the channel decoder in a first mode. The selection signal may be received by the input port and the channel decoder in a second mode.